cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Mentor
Mentor
11,650 Views
Registered: ‎06-09-2011

Where must connect ODELAY2 output

Jump to solution

Hi,

I am trying to postpone a signal going out of my Kintex-7 FPGA. I am using ODELAY2. The problem is that if I connect its output to output signal I receive some errors and PAR fails. I am wondering where I should connect the output of ODELAY2?

My Instantiation:

ODELAYE2_inst : ODELAYE2
   generic map (
      CINVCTRL_SEL 	=> "FALSE",				-- Enable dynamic clock inversion (FALSE, TRUE)
      DELAY_src=> "ODATAIN",			-- Delay input (ODATAIN, CLKIN)
      HIGH_PERFORMANCE_MODE => "TRUE",		-- Reduced jitter ("TRUE"), Reduced power ("FALSE")
      ODELAY_TYPE 	=> "FIXED",				-- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
      ODELAY_VALUE 	=> 20,					-- Output delay tap setting (0-31)
      PIPE_SEL 		=> "FALSE",				-- Select pipelined mode, FALSE, TRUE
      REFCLK_FREQUENCY => 200.0,				-- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
      SIGNAL_PATTERN => "DATA"				-- DATA, CLOCK input signal
   )
   port map (
--      CNTVALUEOUT 	=> "00000",				-- 5-bit output: Counter value output
      DATAOUT 			=> sDelayedSCLK,		-- 1-bit output: Delayed data/clock output
      C 					=> sCLK_DIV,			-- 1-bit input: Clock input
      CE 				=> '0',					-- 1-bit input: Active high enable increment/decrement input
      CINVCTRL 		=> '0',					-- 1-bit input: Dynamic clock inversion input
      CLKIN 			=> sDLYCTRL_CLK,		-- 1-bit input: Clock delay input
      CNTVALUEIN 		=> "00000",				-- 5-bit input: Counter value input
      INC 				=> '0',					-- 1-bit input: Increment / Decrement tap delay input
      LD 				=> '0',					-- 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
														-- VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN

      LDPIPEEN 		=> '0',					-- 1-bit input: Enables the pipeline register to load data
      ODATAIN 			=> sSCLK,				-- 1-bit input: Output delay data input
      REGRST 			=> '0'					-- 1-bit input: Active-high reset tap-delay input
   );
	oSCLK <= sDelayedSCLK;

I receive below error:


ERROR:Route:471 -
This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
routed:
Unrouteable Net:sDelayedSCLK

 

Could anybody please advise?

 

Thanks in advance,

Hossein

 

Thanks,
Hossein
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
22,360 Views
Registered: ‎06-14-2012

Re: Where must connect ODELAY2 output

Jump to solution

How is sDelayedSCLK connected? 

 

Also, The ODELAYE2 element is only available in the HP banks that support IOSTANDARDS up 1.8V.  It is not available in the HR banks that support LVCMOS25.

There is something in the design thats not allowing this. Otherwise your instantiation looks ok.

 

Regards

Sikta

View solution in original post

5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
22,361 Views
Registered: ‎06-14-2012

Re: Where must connect ODELAY2 output

Jump to solution

How is sDelayedSCLK connected? 

 

Also, The ODELAYE2 element is only available in the HP banks that support IOSTANDARDS up 1.8V.  It is not available in the HR banks that support LVCMOS25.

There is something in the design thats not allowing this. Otherwise your instantiation looks ok.

 

Regards

Sikta

View solution in original post

Highlighted
Mentor
Mentor
11,634 Views
Registered: ‎06-09-2011

Re: Where must connect ODELAY2 output

Jump to solution

i,

Thank you so much for your fast answer. As you see :

oSCLK <= sDelayedSCLK;

it is connecterd directly to an IO pin. oSCLK is defined as output in top entity.

I also checked it with LVCMOS18 pins it still fails?! 

Thanks,
Hossein
0 Kudos
Highlighted
Mentor
Mentor
11,610 Views
Registered: ‎06-09-2011

Re: Where must connect ODELAY2 output

Jump to solution

Hi @siktap,

I had some tests and observed that there may be a limitation on IOB sites which are ODELAY capabale, is that right?

I removed location constraint from my ucf and saw that in an automatic placement - ofcourse for HP banks - it can route it?!

However, I couldn't find a document specifying which locations are ODELAY capable. Do you know where I should look for it?

 

Thanks,

Hossein

Thanks,
Hossein
0 Kudos
Highlighted
Mentor
Mentor
11,601 Views
Registered: ‎06-09-2011

Re: Where must connect ODELAY2 output

Jump to solution

Hi @siktap,

Finally I could find the source of problem. I was not just using HP bank for ODELAY?!. Very simple!.

I only needed to use IOs from HP banks. I am using Kintex-7 325T FFG900 package. According to 7-series package IO document I realized which Banks are HP banks!.. Below figure shows HP banks in that package:

HP Banks.jpg

I could successfully run the project without failure after I placing that pin in HP Banks.

 

Thanks,

Hossein

Thanks,
Hossein
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
11,588 Views
Registered: ‎06-14-2012

Re: Where must connect ODELAY2 output

Jump to solution

Thanks @embedded for your update. Glad that I was helpful.

 

Regards

Sikta

0 Kudos