I want to debug the FPGA on a hardware processing platform with Z7030 device in real time. I build a block design with a BRAM Controler as slave of Zynq Processing System. As I I encounter an error when I try to send a "mwr 0x40000000 0x0" command through the XMD debug tool. (In the hardware part, I have added a BRAM Controller as a slave module for zynq-core. The BRAM controller has a base address of 0x40000000).
Error: AP transaction error (DP CTRL_STAT=0xf0000021)
I have tried the same design on a ZC706 board configured in JTAG mode. The transaction will be successfully made. I am wondering if the error is caused by the SD boot mode or by any other settings made on the Z7030 board?