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rickwen77
Visitor
Visitor
5,023 Views
Registered: ‎09-02-2016

Why ISERDES can only convert 10 or 14 bit wide signals?

Hi,

 

I'm trying to use iserdes2 to create 12-bit signal by serial-to-parallel convert. But in ug471, it said only 10 or 14 bit are supported when using two cascaded iserdes2. 

 

My question is whether I can use two iserdes2 to create a 12-bit signal?

 

Thanks

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balkris
Xilinx Employee
Xilinx Employee
5,016 Views
Registered: ‎08-01-2008

This is architecture limitation of target device. You can do serdes cascading . Check this related XAPP it may help you

http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf

Thanks and Regards
Balkrishan
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rickwen77
Visitor
Visitor
4,950 Views
Registered: ‎09-02-2016

Balkrishan,

 

I'm using 7-series FPGAs and xapp1064 is for spartan6. Actually I found this

http://www.xilinx.com/support/documentation/application_notes/xapp1017-lvds-ddr-deserial.pdf

 

But it still doesn't tell why 1 to 12 conversion can't be implemented by two cascaded iserdes.

 

Thanks

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