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Adventurer
Adventurer
7,812 Views
Registered: ‎11-25-2015

Why my app_rdy signal is kept low permanently in the middle of the process?

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Hello all,

 

I'm working on a DDR3 project, and I'm using a MIG to generate a memory controller. The software is Vivado 2014.2, the FPGA model is V7 (xc7vx485tffg1927-2).

Everyting works fine in the simulation, the MIG can read all the data out successfully. However, the reading process

stucks and the 'app_rdy' signal is pulled down permanently while I'm running my code on the board using chipscope as you can see in the screenshots.

simulation.PNG

simulation.PNG

 

simulation.PNG
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1 Solution

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Xilinx Employee
Xilinx Employee
14,827 Views
Registered: ‎07-11-2011

Re: Why my app_rdy signal is kept low permanently in the middle of the process?

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@derickshi, MIG does not suport timing simulations, so we do not recommend that flow.

 

If the IP works fine in simulation I would recommend to cross check if your board has any issue.

Please use Xilinx standalone example design and see if it behave the same way.

Double check all the basic things like power, terminations, clocking and reset.

When app_rdy went low permanently probe your board to confirm if DQS is togging

 

Hope this helps

 

-Vanitha

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4 Replies
Moderator
Moderator
7,806 Views
Registered: ‎07-01-2015

Re: Why my app_rdy signal is kept low permanently in the middle of the process?

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Hi @derickshi,

 

Are you using post-implementation timing simulation?

If not please verify the output of post-implementation timing simulation.

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
7,749 Views
Registered: ‎11-25-2015

Re: Why my app_rdy signal is kept low permanently in the middle of the process?

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I'll try it, thanks!
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Xilinx Employee
Xilinx Employee
14,828 Views
Registered: ‎07-11-2011

Re: Why my app_rdy signal is kept low permanently in the middle of the process?

Jump to solution

@derickshi, MIG does not suport timing simulations, so we do not recommend that flow.

 

If the IP works fine in simulation I would recommend to cross check if your board has any issue.

Please use Xilinx standalone example design and see if it behave the same way.

Double check all the basic things like power, terminations, clocking and reset.

When app_rdy went low permanently probe your board to confirm if DQS is togging

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Observer ssummerq
Observer
635 Views
Registered: ‎07-23-2018

Re: Why my app_rdy signal is kept low permanently in the middle of the process?

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Have you solved the problem? I meet the problem like this .Thank you very much!

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