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374786788
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Registered: ‎11-09-2016

X7CV2000T GTX schematic design

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Hi,
    I'm on a circuit board schematic design based on XC7V2000T. In my design, I use bank 112 and bank 113 to connect to a PCIe Cable. And I doesn't use bank 114 or 115.
    I have read the datasheet ug476, but I can't understand very well. the datasheet says "In current members of the 7 series family, all GTX/GTH transceiver Quads are located in a single column along one side of the die." and "If an entire GTX/GTH column is not used, MGTAVTTRCAL and MGTRREF should be tied to ground."
    I want to ask: (1)If the "column" in these two sentence has the same meaning. (2)I want to know if bank 112 bank 113 are not in a same column with bank 114 and bank 115 . (3)And If I only use bank 112 and bank 113, how can I connect the pin in bank 114 and bank 115?
    According to my description, (Plan 1): If I can connect the pin MGTAVTTRCAL_115 and MGTRREF_115 which are in bank 115 to GND and connect all G11 power supply pin(MGTAVCC_G11, MGTAVTT_G11, MGTVCCAUX_G11) to GND or leave this power pins unconnect? (Plan 2): Or I still connect MGTAVTTRCAL_115 to MGTAVTT and to a 100Ω resistor that is also connected to MGTRREF_115, and connect all power supply pins in G11(bank 114 bank 115) to their power plane. The two ways which is best?
    The file below is the relevant schematic. Please help me to check whether the design is correct and which is better(more safety).

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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @374786788,

 

If you refer attached snapshot, you can find that Bank 112 and Bank 113 are in SLR0 and Bank 114 and Bank 115 are in SLR1.

MGTAVTTRCAL for SLR1 is located in Bank 115 whereas MGTAVTTRCAL for SLR0 is located in Bank 112. So since you are not using Bank 114 and 115, you can connect MGTAVTTRCAL_115 as suggested in user guide considering them to be unused.

 

The important consideration which should be followed is bank in which RCAL circuit is located must be powered on. So out of Bank 112 and 113 even if you are not using Bank 112, you need to power it on since RCAL is located in it.

 

Hope this clarifies the confusion. 

Regards,
Ashish
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ashishd
Xilinx Employee
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Registered: ‎02-14-2014

Hello @374786788,

 

Can you let us know the package which you are using? Is it FHG1761 or FLG1925 ?

Regards,
Ashish
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374786788
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The package I use is FLG1925
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374786788
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The package  is FLG1925. Could you give me some suggestion?

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ashishd
Xilinx Employee
Xilinx Employee
8,700 Views
Registered: ‎02-14-2014

Hello @374786788,

 

If you refer attached snapshot, you can find that Bank 112 and Bank 113 are in SLR0 and Bank 114 and Bank 115 are in SLR1.

MGTAVTTRCAL for SLR1 is located in Bank 115 whereas MGTAVTTRCAL for SLR0 is located in Bank 112. So since you are not using Bank 114 and 115, you can connect MGTAVTTRCAL_115 as suggested in user guide considering them to be unused.

 

The important consideration which should be followed is bank in which RCAL circuit is located must be powered on. So out of Bank 112 and 113 even if you are not using Bank 112, you need to power it on since RCAL is located in it.

 

Hope this clarifies the confusion. 

Regards,
Ashish
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374786788
Visitor
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Registered: ‎11-09-2016

Hello 

 

Thank you for your reply. According to your advice, I should connect MGTAVTTRCAL_115 and MGTRREF_115 to GND, and still power the bank 114 and bank 115 on. The following schematic below is according to your suggestion, if I understand the right?

 

power_bank.png

bank112&bank113.png

bank114&bank115.png

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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @374786788,

 

It should be fine even if power supply for bank 114 and 115 is connected as per user guide considering them to be unused. This is because those two quads are completely not used in your design.

Regards,
Ashish
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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @374786788,

 

Did the information address your query?

Regards,
Ashish
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374786788
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Yeah, thank you very much!
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lm1993
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Registered: ‎06-24-2018
Hello,

I am also on a circuit board schematic design based on XC7V2000T-2FHG1761I, but I am a freshman in this field. Additionally, this is a very complex device. So would you please help me and send me your schematic design? I will appreciate it very much if I have chance to refer to your design. My email address is 1501214300@pku.edu.cn. Thank you very much!
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