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Observer x_abacadaba
Observer
791 Views
Registered: ‎12-21-2017

XADC DRP single channel continuous mode vp_vn problem

I've read numerous posts on here regarding the xadc and drp and have tried the various solutions provided with no improvement in results.  Here is a description of what is going on:

 

I'm attempting to use the xadc with the drp interface, single vp_vn channel continuous mode as a proof of concept that will eventually scale up to use more of the xadc channels in sequencing mode.  I'm using a MicroZed7010 with the Avnet IOCC card and the Xilinx AMS101 with jumpers configured for unipolar mode connected to a function generator, for early prototyping.  Presently I've configured a simple system bd design with the xadc configured in single channel continuous mode.  I've added eoc_out, drdy_out, Dout[], busy_out, reset, and the channel_out[]  signals to the ILA.  I use a simple hello world program generated with SDK to bring the PS out of reset. This is what the BD looks like:

 

xadc_drp_bd.png

FCLK_CLK0 is 100MHz.

 

Here is the configuration for the xadc core:

xadc_cfg.png

 

I've selected vp_vn on the single channel tab as well.  The problem that I am seeing is that when I load up the design and run the hello world app, and debug using the ILA, the Dout values always show up as zero.

 

The channel shows up as 0x03 which is the correct value to select the vp_vn register value, and the eoc_out, busy, and drdy all sequence correctly as per the timing in the xadc users guide.  I also ran the reset (the inverted one that goes to the xadc core) signal to an LED to try and get some sanity check that it comes out of reset.  I can see that when I first load the design and the PS is in reset and that my LED indicates that the xadc is also in reset.  When I run a simple program on the board, the led changes state and I see the ILA will trigger on the eoc_out signal.

 

Here are some other things that I've tried to debug this issue based on other postings on this forum:

  • Verified that I can see a sine wave that matches my function generator output in the dashboard if I hook up the xadc in hw manager and monitor the vp_vn signals
  • Programmed my design into flash and set-up the board to boot from qspi with no jtag cable connected (to ensure that jtag is not interfering)
  • Brought all signals out to a logic analyzer and verified that they match the behavior that I am seeing in the ILA and what is expected in the xadc ug; they do match yet the Dout values are always zero.
  • I measured the frequency of the eoc_out signal and it toggles at ~961.5KHz just like the xadc IP core configuration gui indicates it will be.

So I'm not really sure what else to try here?  Any help would be greatly appreciated as my forward progress has stopped.

 

Thanks.

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2 Replies
Moderator
Moderator
763 Views
Registered: ‎04-18-2011

Re: XADC DRP single channel continuous mode vp_vn problem

so it looks like it is converting if you see the waveform plotting over JTAG. 

 

I would encourage you to try something like this:

 

Add the below FSM to the design.

Hard Code the DADDR to the VP/VN register. 

Try drive fsm_start_rd with the EOC 

 

always@(posedge dclk)begin
if(rst)begin
state <= idle;
end
else
state <= next_state;
end

always@* begin
case(state)
idle: begin
den <= 1'b0;
dwe <= 1'b0;
if(fsm_start_rd)
next_state <= read;
else if(fsm_start_wr)
next_state <= write;
else
next_state <= idle;
end
read: begin
den <= 1'b1;
dwe <= 1'b0;
next_state <= idle;
end
write: begin
den <= 1'b1;
dwe <= 1'b1;
next_state <= wait_on_drdy;
end
wait_on_drdy: begin
den <= 1'b0;
dwe <= 1'b0;
if(drdy)
next_state <= idle;
else
next_state <= wait_on_drdy;
end
endcase
end

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Observer x_abacadaba
Observer
726 Views
Registered: ‎12-21-2017

Re: XADC DRP single channel continuous mode vp_vn problem

Thanks for the advice.  I'll see if this sheds any light on the situation and post a follow-up.

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