07-18-2019 08:41 AM
I'm using a Basys 3 board with Artix-7, testing some XADC issues. When I configure continuous mode and simultaneous sampling for two channels (6 and 14) only, looking at EOS and EOC I see both at the same time in a distance depending on the number of averaged values (e.g. for 64 values every 66,5 µs, having 1 MHz sampling rate) - fine. When I add two more channels (7 and 15), I find the EOC pulses roughly in double distance, i.e. in the example 133 µs. There is also an EOS pulse with every EOC. But the second EOS pulse occurs only a microsecond before the EOC. According the description in table 1-2 in UG480_7Series_XADC.pdf, I would expect the second EOS roughly in the middle between two EOC. Could somebody explain what happens here?
07-22-2019 04:16 AM
The EOC should occur twice within the EOS period. The End of Conversion (EoC) should pulse when the 6/14 channels are finished being converted, then the End of Conversion should pulse a second time when the 7/15 channels are finished. The End of Sequnce should pulse at the same time as the second EoC if these are the only two in the sequence.
How are you capturing the EoC and EoS signals? Is it in an ILA, can you share a grab from the ILA?
07-23-2019 01:04 AM
no, I don't use ILA up to now, I simply use output pins and an osci (faster for simple tests than adapting and running a simulation). The picture attached shows eos (blue) and eoc (red). The config of the XADC is:
INIT_40 => X"2000" -- averaging 64 samples
INIT_41 => X"4000" -- simultaneous sampling
INIT_42 => X"0400" -- division ratio: system clock 100 MHz, sampling rate 1 MHz
INIT_48 => X"0000"
INIT_49 => X"00C0" -- when simultaneous sampling: channels 6 and 14; 7 and 15 - the four channels at Basys 3
INIT_4A => X"0000"
INIT_4B => X"C0C0" -- averaging channels 6, 7, 14, 15
As one can see, the first EOC is only 1 µs before the second one, which comes at the same time as EOS.
Funny new fact I just discovered: When using the configuration above, connecting only input channel 6 of the Basys 3 (7, 14, 15 left open) and continuously monitoring the status registers, I found that registers 6 AND 7 change by changing input 6 (same for 14 and 15 when input only 14). Input channels 7 or 15 are not causing any change in the registers. So it seems that only two channels (6 and 14) are really sampled, and the result is written twice in two different registers, which would explain a little the EOC/EOS pulses I can see.
btw: I did the config manually, but the wizzard also gives me that setting. Anyway, I don't completely trust the wizzard any more - the wizzard also generates configurations for event-driven mode including averaging without even a warning, but this combination doesn't work (no EOS/EOC at all) - see reply: https://forums.xilinx.com/t5/Other-FPGA-Architectures/XADC-Event-driven-sampling-with-averaging/m-p/590306#M9921. I already wrote an email to Xilinx regarding this issue, but up to now there was no answer. Therefore, simultaneous sampling of two channel combinations including average might be another case which doesn't work. I will test without averaging.
07-23-2019 08:14 AM
Funny fact even funnier: I wrote above that registers 6 and 7 change by changing input 6 (same for 14 and 15 when input only 14). I realised that I missed to connect channels 7 and 15. After adding this connection, when having just one input connected to a signal source at the pin, the other inputs left open: Inputs 6 and 7 will cause changes in registers 6 and 7, no matter which of the inputs is used. The same for channels 14 and 15. ???
Testing without averaging results in no change.
07-26-2019 04:39 AM
So this matches simulation, when you are averything the EOC does not complete until all the samples have been taken.
The first 63 samples of each channel the EOC does not pulse, then on the 64 of channel for Aux6 will cause EOC to pulse, the next sample is the 64 of Aux7 causing EOC to pulse a second time, and EOS at the same time.