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Registered: ‎09-25-2019

XADC Event Mode Sampling Control

I am designing a sequencer to perform event-driven sampling / single-pass sequence of unipolar conversions of 3 VAUX inputs, followed by a Single-Channel (Seq Off) TEMP conversion.  I have questions.

First, in event-driven mode, when does the  acquisition phase start for the first conversion? Does the first acquisition start on the setting of the Config1 SEQ field to x"01" (Single-Pass Mode), or is a dummy conversion needed? 

UG480 Figure 5-2 shows Acq Time (N) starting on falling-edge EOC/EOS, and Conversion Time (N) start on first ADCCLK after CONVST, but Continuous Sampling Figure 5-2 shows Conv time for (N) starting on rising Busy, and Acq time for (N+1) on the next ADCCLK falling edge. Is Figure 5-2 incorrect, are the Acq Time for N and Conv time for N concurrent ?  

When does Input Mux switch change, on the falling edge of Busy? 

Does the CONFIG1:SEQ field need to be written to x"0011" Single-Channel, before the SEQ field write to x"0001" Single-Pass or is the CONFIG1:SEQ field set to x"0011" on the completion Single-Pass Seq?

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Registered: ‎04-18-2011

Hi @greg.lozes 

Maybe take a step back and explain why you need to use event driven mode if as you say you are designing a sequencer to sample 3 AUX and a temperature. 

You won't get a more efficient sequencer than one inside the XADC. 

You can have the sequencer on and use event mode to sample if you wish. 

I can answer your questions here:

First, in event-driven mode, when does the  acquisition phase start for the first conversion? Does the first acquisition start on the setting of the Config1 SEQ field to x"01" (Single-Pass Mode), or is a dummy conversion needed? 

Single Pass Mode does a single pass through the sequence and just stops after that. I don't know why you would want to use it here. 

I'd say once the XADC comes out of reset it is straight away in acquisition mode so whatever the internal channel select mux is set to is being acquired. 

UG480 Figure 5-2 shows Acq Time (N) starting on falling-edge EOC/EOS, and Conversion Time (N) start on first ADCCLK after CONVST, but Continuous Sampling Figure 5-2 shows Conv time for (N) starting on rising Busy, and Acq time for (N+1) on the next ADCCLK falling edge. Is Figure 5-2 incorrect, are the Acq Time for N and Conv time for N concurrent ?  

I reckon that the figure 5-2 has a typo here. The acquistion time in event mode for N+1 should be happenning during the conversion of N

In general it should be like this in either mode. 

Acquire N+1 after the the conversion of N begins. 

Conversion of N is done

Have a quite time of 4 ADC Clocks to allow the N+1 to settle. Then repeat for the next channel in the sequence. 

When does Input Mux switch change, on the falling edge of Busy? 

It should change at the start of the acquisition phase 

Does the CONFIG1:SEQ field need to be written to x"0011" Single-Channel, before the SEQ field write to x"0001" Single-Pass or is the CONFIG1:SEQ field set to x"0011" on the completion Single-Pass Seq?

I don't know why this scheme is being proposed. Why go from single channel to single pass?
Changing the sequencer is not really a great idea because as you can see the converter is always acquiring the next channel. So it can't just dump that acquistion for a change of sequencer mode. 
If you go from single channel mode to a sequencer mode for example you would have to convert and flush out the previous acquistion. 
 
In the end I think you need to explain what the motivation for what you are trying to do here is. 
 
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