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Visitor pedro4
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Registered: ‎07-14-2017

XADC Invalid channel ouput

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Hello. I was wondering what could cause the XADC to output channel 9 (I mean, the CHANNEL_OUT[4:0] output). Looking at UG480 p45, it says anything between 9 and 12 is "Invalid channel selection". I used the XADC wizard. Also, EOC is always 0 and DRDY_OUT is always 1. What could the reason be? Thank you!

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Visitor pedro4
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Registered: ‎07-14-2017

Re: XADC Invalid channel ouput

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@chapman

 

It's finally working like charm! That was the problem from the beginning, the JTAG port. It was being JTAG-accesed and that made the XADC behave as it wasn't intended to. So I decompiled the dtb from Xillinux, removed the entry of the XADC and it's not being JTAGLOCKED anymore.

 

Thanks for everything chapman.

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Xilinx Employee
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Registered: ‎09-05-2007

Re: XADC Invalid channel ouput

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You are using the XADC Wizard but that doesn't tell us anything out the way you have configured it, your intentions or how you have then included the IP in your design. I think you are best to ignore the CHANNEL output until you have established basic communication with XADC using either AXI or the DRP depending on what you have configured. No activity on DRDY implies that nothing is communicating with XADC yet.  

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Re: XADC Invalid channel ouput

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@chapman

Sorry, I tried to edit my first post to add that information but I couldn't see any button.

 

I'm using a ZedBoard. The interface is DRP. Also I set it up as Channel Sequencer (continuous mode 3 channel: VP/VN, vaux0 and vaux8). I'm basically trying to write the conversion to a FIFO, so I'm using EOC as DEN, and CHANNEL as DADDR (this way is recommended in UG480). Then I connect the DOUT from the XADC to DIN from FIFO and DRDY from XADC to WR_EN from FIFO. Then this FIFO is read by Xillybus and collect the data in Xillinux.

 

This is the config for the XADC:

INIT_40 => X"1000", -- config reg 0
        INIT_41 => X"21AF", -- config reg 1
        INIT_42 => X"0400", -- config reg 2
        INIT_48 => X"0801", -- Sequencer channel selection
        INIT_49 => X"0101", -- Sequencer channel selection
        INIT_4A => X"0800", -- Sequencer Average selection
        INIT_4B => X"0101", -- Sequencer Average selection
        INIT_4C => X"0000", -- Sequencer Bipolar selection
        INIT_4D => X"0000", -- Sequencer Bipolar selection
        INIT_4E => X"0000", -- Sequencer Acq time selection
        INIT_4F => X"0000", -- Sequencer Acq time selection
        INIT_50 => X"B5ED", -- Temp alarm trigger
        INIT_51 => X"57E4", -- Vccint upper alarm limit
        INIT_52 => X"A147", -- Vccaux upper alarm limit
        INIT_53 => X"CA33",  -- Temp alarm OT upper
        INIT_54 => X"A93A", -- Temp alarm reset
        INIT_55 => X"52C6", -- Vccint lower alarm limit
        INIT_56 => X"9555", -- Vccaux lower alarm limit
        INIT_57 => X"AE4E",  -- Temp alarm OT reset
        INIT_58 => X"5999",  -- Vccbram upper alarm limit
        INIT_5C => X"5111",  -- Vccbram lower alarm limit
        INIT_59 => X"5555",  -- Vccpint upper alarm limit
        INIT_5D => X"5111",  -- Vccpint lower alarm limit
        INIT_5A => X"9999",  -- Vccpaux upper alarm limit
        INIT_5E => X"91EB",  -- Vccpaux lower alarm limit
        INIT_5B => X"6AAA",  -- Vccddro upper alarm limit
        INIT_5F => X"6666",  -- Vccddro lower alarm limit
        SIM_DEVICE => "ZYNQ",
        SIM_MONITOR_FILE => "design.txt"

 

Thank you!

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Xilinx Employee
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Registered: ‎09-05-2007

Re: XADC Invalid channel ouput

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@pedro4

 

My quick analysis of those INIT values does indeed suggest that you have configured the channel sequencer to cover your three channels and it will also include calibration.

 

It looks like the clock division factor is 4 but I don't know what your input clock is. Hopefully you are driving DCLK with something; I think the Zedboard provides a 100MHz clock to the PL so that would be Ok and of course you would need the same clock to be applied to your FIFO all distributed via a clock buffer etc.

 

Given your connections, DRDY activity will depend on DEN activity and hence it all relies on EOC activity so focus on looking for that first. Do you have a probe attached to EOC or are you currently assuming nothing is there?

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Registered: ‎07-14-2017

Re: XADC Invalid channel ouput

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@chapman

Indeed, I set up calibration. Also channel average (16).

 

The clock division is 4, and in the XADC wizard I put 100 MHz for DCLK so that would mean ADCCLK is 100/4=25 MHz. Zedboard provides a 100 MHz clock signal but Xillybus forces you to use another signal, bus_clk, with every IP core you instantiate so my FIFO and the XADC are both fed with that bus_clk. I've been reading the documentation and it is said to be 100 MHz so that wouldn't be a problem either (I don't have a way of physically checking it though).

 

What I'm doing to check all those values is to write them directly to the FIFO. I tried using some ILA but Xillybus seems to mess with JTAG and ILA seems to usa that so I don't get proper results. But doing what I mentioned (writing the values to the FIFO) seems fine, or maybe it's not? For example, I take DRDY and do something like DOUT <= "000000000000000" & DRDY, so it writes every clk period the value of DRDY. The same with EOC. DRDY is always 1 and EOC is always 0.

 

Thanks!

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Visitor pedro4
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Re: XADC Invalid channel ouput

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Btw: if you'd like to have a look at my project (maybe you need more information than what I'm giving), I can share it with you via PM

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Voyager
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Registered: ‎06-24-2013

Re: XADC Invalid channel ouput

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Hey @pedro4,

 

May I ask why you want to do the read-out in PL when you then transfer the data to the PS anyway?

(I'm not implying that you shouldn't do it, I'm just curious :)

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Xilinx Employee
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Registered: ‎09-05-2007

Re: XADC Invalid channel ouput

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@pedro4

 

I don't feel entirely comfortable with your 'probing' scheme. Even if assume you have connected signals to your FIFO as you intended there is the matter of how fast you read from the FIFO and what happens if/when the FIFO becomes full.

 

Anyway, no EOC pulses and DRDY permanently High (1) doesn't make any sense. DRDY should only go High following a DEN and if you have connected EOC to DEN then that suggests that EOC at least pulsed High once.

 

One idea; what have you connected DWE to? You only intend to read so it should be tied Low (0). If it were High (1) then you would be writing and that could lead to all kinds of unexpected behaviour.  

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Registered: ‎07-14-2017

Re: XADC Invalid channel ouput

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@chapman

 

Yes, I agree. That's not the best way to check signals but what other ways do I have left? Maybe I could make a simple finite state machine and turn on a LED if EOC ever goes high?

 

Indeed, I connected DWE to 0. If you want to take a look at my top_xadc:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_xadc is
    Port(
        clk : IN std_logic;
        reset : IN std_logic;
        vp_in           : in  STD_LOGIC;
        vn_in           : in  STD_LOGIC;
        vauxp0          : in  STD_LOGIC;
        vauxn0          : in  STD_LOGIC;
        vauxp8          : in  STD_LOGIC;
        vauxn8          : in  STD_LOGIC;        
        enable : OUT std_logic;
        dout : OUT std_logic_vector(31 downto 0)
    );
end top_xadc;

architecture Behavioral of top_xadc is
component xadc_wiz_0 is
   port
   (
    daddr_in        : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
    den_in          : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
    di_in           : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
    dwe_in          : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
    do_out          : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
    drdy_out        : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
    dclk_in         : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
    reset_in        : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
    jtagbusy_out    : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
    jtaglocked_out  : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
    jtagmodified_out : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred    
    vauxp0          : in  STD_LOGIC;                         -- Auxiliary Channel 0
    vauxn0          : in  STD_LOGIC;
    vauxp8          : in  STD_LOGIC;                         -- Auxiliary Channel 8
    vauxn8          : in  STD_LOGIC;
    busy_out        : out  STD_LOGIC;                        -- ADC Busy signal
    channel_out     : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
    eoc_out         : out  STD_LOGIC;                        -- End of Conversion Signal
    eos_out         : out  STD_LOGIC;                        -- End of Sequence Signal
    alarm_out       : out STD_LOGIC;                         -- OR'ed output of all the Alarms
    vp_in           : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
    vn_in           : in  STD_LOGIC
);
end component;

signal channel : std_logic_vector(4 downto 0);
signal daddr : std_logic_vector(6 downto 0);
signal dout_aux : std_logic_vector(15 downto 0);
signal eoc : std_logic;
--signal jtaglocked : std_logic;
begin

    xadc : xadc_wiz_0
       port map
        (
         daddr_in        => daddr,
         den_in          => eoc,
         di_in           => (others => '0'),
         dwe_in          =>'0',
         do_out          =>dout_aux,
         drdy_out        =>enable,
         dclk_in         =>clk,
         reset_in        =>reset,
         jtagbusy_out    =>open,
         jtaglocked_out  =>open,
         jtagmodified_out =>open,
         vauxp0          =>vauxp0,
         vauxn0          =>vauxn0,
         vauxp8          =>vauxp8,
         vauxn8          =>vauxn8,
         busy_out        =>open,
         channel_out     =>channel,
         eoc_out         =>eoc,
         eos_out         =>open,
         alarm_out       =>open,
         vp_in           =>vp_in,
         vn_in           =>vn_in
        );
        
    daddr <= "00" & channel;
    dout <= dout_aux(7 downto 0) & dout_aux(15 downto 8) & x"0000";
    
end Behavioral;

 

When I want to test the value of any signal, I just change the line

dout <= dout_aux(7 downto 0) & dout_aux(15 downto 8) & x"0000";

For whatever I want to write to the FIFO.


I've been trying to make this work for 2 months and no matter how many times I try to re-do the code and check it, everything seems just fine to me.

 

In case you want to take a look at the project, here's a link to download it. (Everything is under 'vhdl' directory).

 

Thanks.

 

@hpoetzl

 

It's a requirement I must meet, so I can't decide whether or not to do the read-out in PL. If I could directly use the PS, I would (although I'm not sure it's working on Xillybus in spite of the fact that I can "read" values from the XADC).

 

Thanks.

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Xilinx Employee
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Registered: ‎09-05-2007

Re: XADC Invalid channel ouput

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@pedro4

 

Are you certain that you are not asserting reset? I see a 'reset-32' signal in your higher level code but I don't want to understand or guess how that NOT/OR combination drives it. If by any chance you are driving XADC reset High or pulsing it in some way then you could easily be confused so please check (or just drive reset with '0' until you get things working).

 

I have a horrible feeling that you are confusing yourself with you attempt to 'probe' signals. Since you enable the FIFO with DRDY it will only ever sample DRDY when it is High! Likewise, it will only capture other signals when DRDY is High and therefore it would then always capture EOC at a point when it is Low (0).

 

After 2 months then I think it's definitely time to do something simple like use a counter to count EOC pulses and then read that counter (or connect the MSB to an LED).

Ken Chapman
Principal Engineer, Xilinx UK
Visitor pedro4
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Registered: ‎07-14-2017

Re: XADC Invalid channel ouput

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@chapman

 

About the counter, well, it did count! I set up a counter of 8 bits and connect some of the bits to a few LEDs and they all turned on, plus I wrote the counter to the FIFO and well, you can see by yourself:

 

Captura.PNG

 

So that means EOC is being actually asserted

 

About the reset, that was my mistake to use that reset cause it's held high while I'm not reading the FIFO, although it changes to low when I'm reading it so that means the XADC was being held on reset while I wasn't checking the values being written to the FIFO. So I connected that reset_32 to 0, and I got something different. It seems that now it was converting properly cause I read the values from the FIFO and they made sense but after a few second reading it, the FIFO seemed to be filled with the same garbage as usual.

 

Btw what I'm talking about when I say "reading the FIFO" is that I'm running some code like cat /dev/xillybus_read_32 or hexdump -C /dev/xillybus_read_32 (more exactly, I'm running the latter).

 

So that means it kinda fixed it but not completely. Once I run hexdump, it's filled with garbage and if I do Ctrl+C to stop it and then run hexdump again, I'm not getting good values anymore. It looks like it running hexdump breaks it? or that it holds the XADC on reset? But that isn't possible since I did reset_32<=0 so there's no way it's resetting it.

 

Here's a screenshot so you know what I'm talking about (this is printed by running hexdump -C /dev/xillybus_read_32):

screenshots.png

 

Thank you very much!!

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Visitor pedro4
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Re: XADC Invalid channel ouput

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Sorry, the red square is wrong. Garbage values are everything below the green square
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Xilinx Employee
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Re: XADC Invalid channel ouput

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@pedro4

 

So it was the reset that was causing your problems for 2 months; that really should not have taken that long to discover so I'm glad I suggested it!

 

Note that if you have averaging enabled then the status registers will only be updated once enough samples have been acquired. The reading scheme you are using is triggered by every EOC pulse and therefore this would lead to bursts of identical values being written to your FIFO. Maybe this is the cause of the identical values that you see.

 

I think you can now see that XADC can operate properly as long as you are not resetting it and as such I think you should now focus on the rest of the design including making sure that you are only reading the FIFO when it contains new information and do not allow it to become full. Please mark this thread as solved and start a new one if you have other issues.

 

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Re: XADC Invalid channel ouput

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@chapman

 

When I call those values "garbage values" is not because they're identical (although yes, they are), it's because if you look at them, it would mean the analog input are near 1V, which isn't true at all. And that's because it's still writing the FIFO with values from channel 9, which is an invalid channel. The reset thing only helped for the first values when I first power on the board but it goes back to its anomalous behaviour after that. Also, I've tried disabling averaging and calibration in case those where causing such behaviour but no, it's still the same. I don't care about the XADC values when I'm not reading the FIFO; I need them to be accurate when I'm reading it, and it seems to happen quite the opposite. I also made sure not to write the FIFO if it's full when something like enable_write <= not(full_fifo) and drdy_xadc, this way it won't write when it's full but again, didn't fix anything.

 

Casually, I always get good values till line 7ffh, and if I have 32x4 bits in each line, that is 16 bytes then I'm getting 800h x 16bytes = 32768 bytes but the FIFO is only 512 x 32bytes = 16384 bytes, that means it went full twice without problems and from then on it just "stopped" working.

 

As I see it, it's still the same problem I started the topic with, but if you consider this is solved and that I should start a new one regarding this matter, I'll do it.

 

Thank you again for your help!

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Xilinx Employee
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Re: XADC Invalid channel ouput

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A value close to FFFF could also be a small negative value in twos complement format (i.e. a channel using bipolar mode).

 

Given your previous issues 'probing' signals how exactly are you determining that the XADC is sequencing channel 9? Note that if you are using DRDY pulses to enable writes to your FIFO then you would be sampling CHANNEL at a time when EOC is Low. What matters is the value of CHANNEL when EOC is pulsed High because that is what use are using to initiate the read of status registers. So unless you use a register to capture values of CHANNEL when EOC is High and then feed that captured value into your FIFO you will not be writing valid and meaningful information.

 

XADC has been around a long time now so it's extremely unlikely that it "falls over" after working nicely for a while especially if you have now tied reset Low. I think you need to focus on the rest of your design now. I suggest that you try feeding your FIFO with a 32-bit counter and proving that your design writes and reads the FIFO reliably. I notice in your design that you don't connect the FIFO full status signal to anything which makes me feel uncomfortable.

 

 

  

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Re: XADC Invalid channel ouput

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@chapman

 

I know I could get values close to FFFF if I were in bipolar mode, but I set the mode to unipolar, so that'd mean I'm feeding something close 1V and I'm not doing that.

 

I'm using now the FULL flag from the FIFO along with the DRDY flag from the XADC to assert the WEN from the FIFO.

 

I set the counter to count JTAGLOCKED and it counted 1 pulse, then it went low (I added a small functionalty to the counter that tells me if the tested pulse got stuck waiting for the pulse to go low). I don't think it has something to do with the anomalous behaviour of the XADC but just in case it means something to you.

 

I tried if the FIFO is reading and writing well this way: the counter now is 32 bits, and I'm counting EOC. In the previous post, I said the FIFO was full twice before it started "Malfunctioning" but I was wrong, it was full just once. And it happens the same here, the counter reaches 200h (which is 512, the depth of the FIFO) and the FIFO is full then. Then the counter keeps counting although it can't write to the FIFO due to it being full (as expected). Once I open the FIFO (with hexdump), the FIFO empties and it gets filled again. In the screenshot, you can see there's a jump between 200h and the next count and that's because of what I said, the counter was counting even though it wasn't writing to the FIFO. I also connected the 4 MSB to 4 LEDs so I could see them turn on (it took some time though, it was 32 bits).

 

Sin título.png

So I can assume I'm reading and writing to the FIFO correctly. This is the way I'd expect the XADC to work: it's converting all the time and writes to the FIFO when it's not full. And that's what it does, apparently, because everything is okay until it gets full for the first time, then I keep getting values close to FFFF that doesn't make sense as I explained above (unipolar mode).

 

Also, I tried to write which channels where being converted to the FIFO and it's all good, I keep getting channels 3, 10 and 18 which are VP/VN, Vaux0 and Vaux8 until the FIFO gets full, then all I got is channel 9 as you can see in the next screenshot.

Captura.PNG

 

Thanks!

 

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Xilinx Employee
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Re: XADC Invalid channel ouput

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@pedro4

 

There is no way that the XADC knows when your FIFO is full so unless you have a feedback mechanism that impacts the operation of XADC. It is working autonomously and emitting values unless you are controlling it in some way that I don't know about which you were in the past with that reset signal.

 

Talking of reset signals, your code had that 'reset_32' going to your FIFO as well so are your sure you aren't doing something funny to the FIO as well.

 

It's just too consistent that your issue occurs at the length of your FIFO. Remember that whilst you are reading from the FIFO more data can be written in so I'm surprised you don't at least read 513 values sometimes before it becomes empty.

 

Are you sure that you're not reading the FIFO once it becomes empty? Do you only start reading it once it is full?

 

Prove that XADC is generating CHANNEL 9 at the same time as an EOC. Try detecting this pattern and driving your LED if it occurs (e.g. set a flip-flop if EOC and channel=9).

 

Make sure you are not doing anything with a JTAG application that involves XADC (e.g. something that reads and displays die temperature). JTAG has highest priority unless you disable it in your bit stream.

 

 

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Re: XADC Invalid channel ouput

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@chapman

 

There is no way that the XADC knows when your FIFO is full...

I know the XADC can't know the FIFO is full and I don't really need it to know if it is. I mean, it's okay for me that the XADC is converting and I'm losing the result of that conversion, I'm only interested in the values when I'm reading the FIFO. This is why I'm saying that I'd like the XADC to be converting all the time, no matter if the FIFO is full or not. Unless you tell me the XADC needs to store the values somewhere in order to work properly? Which certainly would be non-sense. I mean, if I enable DEN and the XADC puts data on DOUT, am I forced to do something with that? I don't think so and I haven't read anything like that in UG480 but I might be wrong.

 

Talking of reset signals, your code had that 'reset_32' going to your FIFO...
Yes, actually the reset problem was related to the FIFO, not the XADC. I've just checked it. I couldn't see the first good values of the conversion cause it was resetting the FIFO so the first values disappeared when I opened it to read the content. So currently both the reset to the FIFO and the XADC is set to 0.

 

It's just too consistent that your issue occurs at the length of your FIFO...
I think the same as you on this one. It's weird that it happens exactly with the length of the FIFO.

 

Are you sure that you're not reading the FIFO once it becomes empty?...
Im not reading the FIFO when it's empty. Actually, it's not up to me. Xillybus takes care of it, I just need to connect it with the empty flag from the FIFO and it won't read when EMPTY is asserted.

 

Prove that XADC is generating CHANNEL 9 at the same time as an EOC...
I did what you suggested, I set a flip-flop if channel=9 and EOC=1 and the LED turned on. So this confirms the XADC is acting weird?

 

Make sure you are not doing anything with a JTAG application that involves XADC...
I tried adding this line to the constraints file, but it didn't seem to work as I kept counting 1 JTAGLOCKED pulse.

set_property BITSTREAM.GENERAL.JTAG_XADC Disable [current_design]


Is this the only way to disable JTAG for the XADC?

I don't know, it looks like something is disabling the XADC but I don't understand what could be causing this.

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Xilinx Employee
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Re: XADC Invalid channel ouput

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If you're really getting JTAGLOCKED then that's something you need to investigate further. As well as indicating when JTAG is accessing XADC it can also go High if DCLK stops so are you sure that whatever generates your 'bus_clk' doesn't stop it for whatever reason?

 

I suggest that you program your Flash and have the device come up without anything ever being connected to JTAG to determine if it is something external polling XADC and messing things up. You are relying on the initialisation of XADC in the bit stream to make it perform your auto sequencing so if something else is overwriting those register values it won't be doing what you expect even after JTAG has stopped using it.

 

 

 

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor pedro4
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Re: XADC Invalid channel ouput

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@chapman

 

It's finally working like charm! That was the problem from the beginning, the JTAG port. It was being JTAG-accesed and that made the XADC behave as it wasn't intended to. So I decompiled the dtb from Xillinux, removed the entry of the XADC and it's not being JTAGLOCKED anymore.

 

Thanks for everything chapman.

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