cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
2,987 Views
Registered: ‎06-21-2017

XADC JTAG locking DRP issue

Jump to solution

Hi all,

I ran into an issue with the XADC DRP interface. 

With the Vivado XADC Wizard I generated a simple XADC with Channel Seq., DRP, JTAG arbiter in continuous mode.

Using the method from UG480 p.73 (hooking up EOC/EOS to DEN and CHANNEL to DADDR and DRDY to FIFO_EN) I was able to read all values from the XADC in simulation.

However, this does not work on the hardware ( I am using an Arty Board with xc7a35tcsg324-1). 
I figured that the JTAGLOCKED signal is constantly driven to high ( by wiring it to an external LED ), which leads to the DRP being disabled for the FPGA logic according to UG480 p.51. 

So I disabled JTAG_XADC access (from UG480 p.47) with this command in the xdc:

set_property BITSTREAM.GENERAL.JTAG_XADC Disable [current_design]

This worked, as I can no longer read values from the ADC using the HW Manager / System Monitor. 

But the JTAGLOCKED is still driven to HIGH. 

UG480 p.51 suggests writing 0x0000 to DRP address 0x00 to disable the JTAGLOCKED signal, but I don't know how to do that without an external JTAG access and the FPGA logic DRP interface being blocked by the JTAGLOCKED signal. 

 

Maybe anyone already had this problem or can help me? 

I think it's probably just some kind of misconfiguration. 

 

I'd appreciate any help :) 

Thanks! bzi

 

This is my XADC config generated by the wizard:

INIT_40 => X"8000", -- config reg 0
INIT_41 => X"210C", -- config reg 1
INIT_42 => X"F100", -- config reg 2, dclk is 100 MHz - clkdiv for 16MHz
INIT_48 => X"0900", -- Sequencer channel selection
INIT_49 => X"000F", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B5ED", -- Temp alarm trigger
INIT_51 => X"57E4", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"CA33", -- Temp alarm OT upper
INIT_54 => X"A93A", -- Temp alarm reset
INIT_55 => X"52C6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"AE4E", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit

 

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
4,652 Views
Registered: ‎06-21-2017

Hi guys, just to keep anyone updated with the solution. 

I've had the Xilinx support have a look at it and it was simply a misconfiguration of the ADCCLK clock divider. 

The data sheet says that the ADCCLK (the divided down DCLK) must be in the range 1-26MHz.

In my case I set the CD bits in config register 0x42 to F1 or 241 in decimal.

With a 100MHz DCLK divided by 241 results in the ADC running at 415KHz.

And this will lock up the DRP interface (as described here: https://www.xilinx.com/support/answers/68888.html).

 

Hence, the XADC wizard does not only allow you to configure valid clock dividers but also invalid ones (from 0.41 to 25MHz).

 

I hope this helps anyone who might stumble upon this in the future.

Benjamin

View solution in original post

1 Reply
Highlighted
Visitor
Visitor
4,653 Views
Registered: ‎06-21-2017

Hi guys, just to keep anyone updated with the solution. 

I've had the Xilinx support have a look at it and it was simply a misconfiguration of the ADCCLK clock divider. 

The data sheet says that the ADCCLK (the divided down DCLK) must be in the range 1-26MHz.

In my case I set the CD bits in config register 0x42 to F1 or 241 in decimal.

With a 100MHz DCLK divided by 241 results in the ADC running at 415KHz.

And this will lock up the DRP interface (as described here: https://www.xilinx.com/support/answers/68888.html).

 

Hence, the XADC wizard does not only allow you to configure valid clock dividers but also invalid ones (from 0.41 to 25MHz).

 

I hope this helps anyone who might stumble upon this in the future.

Benjamin

View solution in original post