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Registered: ‎11-12-2019

XADC actual synqronization

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Hi everyone,

I use xadc of artix7 to get adc values of sinusoidal signal to multiply it with internal sinusoidal signals. Therefore, I have to know the exact time of the output time of the XADC. In single-channel mode, XADC IP core gives the actual conversion rate but, I use the channel sequencer mode. I tried eoc_out and data valid signals but I don't know how to introduce these signals. Are there any ways to solve the problem. Thanks.

Regards...

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Registered: ‎01-22-2015

azadozankorkan@anadolu.edu.tr 

I use xadc of artix7 to get adc values of sinusoidal signal to multiply it with internal sinusoidal signals. Therefore, I have to know the exact time of the output time of the XADC.

As I understand, you want to know the delay, TDEL, associated with XADC conversion and with making the XADC output available to your HDL.

The following test can help you determine TDEL:  

  1. Write HDL that tells the FPGA to output a digital pulse, PUL1, at every millisecond-tic of your FPGA internal clock.
  2. Attenuate and route PUL1 to the input of the XADC.
  3. Write HDL that tells the FPGA to output a higher order bit, BIT6, of the XADC output.  
  4. Use an oscope to monitor the outputs, PUL1 and BIT6, from the FPGA.  The time difference between both outputs going high should be a good measurement of TDEL.

Cheers,
Mark

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Registered: ‎01-22-2015

azadozankorkan@anadolu.edu.tr 

I use xadc of artix7 to get adc values of sinusoidal signal to multiply it with internal sinusoidal signals. Therefore, I have to know the exact time of the output time of the XADC.

As I understand, you want to know the delay, TDEL, associated with XADC conversion and with making the XADC output available to your HDL.

The following test can help you determine TDEL:  

  1. Write HDL that tells the FPGA to output a digital pulse, PUL1, at every millisecond-tic of your FPGA internal clock.
  2. Attenuate and route PUL1 to the input of the XADC.
  3. Write HDL that tells the FPGA to output a higher order bit, BIT6, of the XADC output.  
  4. Use an oscope to monitor the outputs, PUL1 and BIT6, from the FPGA.  The time difference between both outputs going high should be a good measurement of TDEL.

Cheers,
Mark

View solution in original post

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Registered: ‎11-12-2019
Thanks, Mark, it looks like a good solution, since XADC has a 1 Ms/s sampling rate, additional internal routes are not so important. I will try your solution.

Regards...
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