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Registered: ‎03-16-2020

XADC in Zynq 7020

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Hello,

I am going to use the Zynq 7020 SoC for a control task where I have 18 analog inputs in total. From the total number of analog inputs are 11 current signals, 2 are voltage signals and 5 are temperature signals. As far as the sampling period of the signals I am going to chose it according to the ascending time constants i.e. current signals sampled with the highest sampling frequency, then voltage signals sampled with lower sampling frequency and temperature signals sampled with the lowest sampling frequency. As far as the signals of current I need to have samples of two pairs of them at the same time due to calculation of the observer of the system. Can anybody give me an advise how to set the XADCs in the Zynq 7020 appropriately? Thanks for any ideas.

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Registered: ‎04-18-2011

Re: XADC in Zynq 7020

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Hi @Steven

There are some things for you to consider here.

First of all there are 16 auxillary analog inputs and a vp/vn input making 17 external inputs.

If you want simultaneous sampling then the auxillary inputs can be sampled in pairs vaux0/vaux8, vaux1/vaux8 and so on.

Also you need to understand that the maximum sample rate of the XADC is one 1Msps, this will be sub divided as the number of channels is increased.The sampling mode can be set to automatic sequencer and it will run through the channels you've selected.

To be honest, trying to change the sequencer on the fly to swap out the lower frequency channels can be tricky because the XADC is always acquiring the next channel in the sequence while it is converting the current one. 

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Registered: ‎04-18-2011

Re: XADC in Zynq 7020

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Hi @Steven

There are some things for you to consider here.

First of all there are 16 auxillary analog inputs and a vp/vn input making 17 external inputs.

If you want simultaneous sampling then the auxillary inputs can be sampled in pairs vaux0/vaux8, vaux1/vaux8 and so on.

Also you need to understand that the maximum sample rate of the XADC is one 1Msps, this will be sub divided as the number of channels is increased.The sampling mode can be set to automatic sequencer and it will run through the channels you've selected.

To be honest, trying to change the sequencer on the fly to swap out the lower frequency channels can be tricky because the XADC is always acquiring the next channel in the sequence while it is converting the current one. 

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Registered: ‎03-16-2020

Re: XADC in Zynq 7020

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Hello klumsde,

thank you for your answer but I do not understand one thing. You have written that the ADC is acquiring next channel during converting the current one. Please can you tell me how is that possible? I thought that ADCA in the XADC module has one sample and hold circuit and ADCB has also one sample and hold circuit i.e. each ADC can start acquisition of next channel after the sample of previous channel has been created.

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Registered: ‎04-18-2011

Re: XADC in Zynq 7020

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The ADC will acquire as it is converting because it has already sampled the voltage onto the sample caps so as it is converting it is free to start acquiring again

xadc_acq.PNG

so in your case with simultaneous selection both ADCs will be acquiring the next sample whilst converting the current one. 

Now one thing you could do is keep the first channel in your sequence fixed always. Then you can modify the sequence directly after the second to last EOC.

xadc_dynamic_sequence.png

 

As long as you keep the first channel in the sequencer fixed, you won't lose any throughput if you do this. 

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Registered: ‎03-16-2020

Re: XADC in Zynq 7020

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I am very sorry but I have been probably still missing something important. My question is based on the idea that the voltage sample on the capacitor has to be present there for the whole conversion time to enable the ADC to create the digital version of the sample correctly (in case I start charging the capacitor during conversion I will corrupt the sample from previous acquisition). From the first sentence of your answer I guess that there are two memory capacitors associated to one ADC. In case first of them contains sample from acquisition of current channel the second one is free and can be used for acquisition of the next channel. Is that the case?

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Registered: ‎04-18-2011

Re: XADC in Zynq 7020

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the circuit itself is proprietary. 

But I expect there is some sort of redundancy in terms of the sample cap. 

This arrangement significantly reduces the requirements for the analog front end driving the XADC, the benefit of which is you have a long time to acquire and settle the signal.

This application note is a good reference for driving the XADC

https://www.xilinx.com/support/documentation/application_notes/xapp795-driving-xadc.pdf

In this case you need to respect the timing shown in the previous diagram for input acquisitions/conversion

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