UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
5,786 Views
Registered: ‎11-03-2013

XADC module

Jump to solution

Hi all,

 

When I'm using the ug480 reference design for the XADC module (attached), I'm able to read the temperature and voltages from the 160T(and 325T) kintex7 FPGA, but when I try using the XADC module in a block design the temperature bus ("temp_out") is always zero and the "busy" is always high. When I'm trying to read the data using a microblaze cpu, I get the same result, the temperature readout is also zero.

 

This is the XADC part of the block design:

123.png

What could cause the reference design to work but the block design not to work?

The clock is running and the reset is not active.

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
10,332 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution

The same reset is connected to other functioning modules (also active low) in the block design, so this isn't the problem.

 

Anyway, I used the reference design and tweaked the XADC module created by the wizard to get pretty much the same parameters, i.e. :

 

XADC_INST : XADC
generic map(
INIT_40 => X"B000", -- config reg 0
INIT_41 => X"21F0", -- config reg 1
INIT_42 => X"0800", -- config reg 2
INIT_48 => X"4701", -- Sequencer channel selection
INIT_49 => X"0000", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B877", -- Temp alarm trigger
INIT_51 => X"57E4", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"B363", -- Temp alarm OT upper
INIT_54 => X"A425", -- Temp alarm reset
INIT_55 => X"52C6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"A93A", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt")

 

This made the XADC work (in the block design as well), but in a different mode than I originally intended ("channel sequencer" instead of "single channel"). I only need the temperature of the FPGA and the voltages are not important to me right now, but I can live with this solution.

0 Kudos
9 Replies
Scholar austin
Scholar
5,758 Views
Registered: ‎02-27-2008

Re: XADC module

Jump to solution

g,

 

When either design is running, what do you get using the hardware_manager in Vivado reading the XADC from the (usb) JTAG port?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Explorer
Explorer
5,754 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution
When running the ug480 reference design I'm getting the correct temperature (~40c), when running the design with the block design inside I'm getting a temperature of -270c
0 Kudos
Scholar austin
Scholar
5,743 Views
Registered: ‎02-27-2008

Re: XADC module

Jump to solution

g,

 

That is good, as it tells us the XADC is not configured correctly, or has no clock, or resetn is asserted (low).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Explorer
Explorer
5,730 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution

Might be, but the design contains other blocks that work just fine. The same clock and reset signals are connected to all of them, so it can't be that.

 

I'm using an AXI interconnect between the microblaze and all other AXI modules. The other modules have full AXI interface, but the XADC has AXI lite interface, could it be an issue?

 

I'm first trying to read the "temp_out" bus but it's all zeros (and busy is always high), then I'm trying to address the module through the software running on the microblaze but I'm getting the same result (all zeros).

 

Are there any configuration needed to start reading the temperature?

0 Kudos
Xilinx Employee
Xilinx Employee
5,716 Views
Registered: ‎09-05-2007

Re: XADC module

Jump to solution

Whilst I'm familiar with using the XADC primitive is an HDL design I confess that I have not used the ‘xadc_wiz’ version with AXI-Lite interface. However, I’m pretty certain that the AXI clock (s_axi_aclk) is being used by all the logic inside the macro including being applied to the ‘DCLK’ of the XADC itself. That makes me wonder what you have done to define the ADCCLK division factor such that ADCCLK falls in the 1 to 26MHz range. Maybe this helps?

Ken Chapman
Principal Engineer, Xilinx UK
0 Kudos
Explorer
Explorer
5,712 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution

In the wizard, this clock is not defined directly.

The AXI clock should be specified (156.25MHz in my case), as well as the desired conversion rate (lets say 200 KSPS).

From those, the acquisition time (clock) is automatically derived ("4" in this case).

The clock divider is also derived automatically and set to "31" so the ADC clock is set to 5.04MHz (automatically as well):

 

xadc.png

 

0 Kudos
Xilinx Employee
Xilinx Employee
5,697 Views
Registered: ‎09-05-2007

Re: XADC module

Jump to solution

So the clock sounds reasonable.

 

Sorry to throw an 'obvious' suggestion at you but it's worth checking the polarity of your reset signal given that 's_axi_aresetn' is active Low (0) whereas the majority of native controls in an FPGA are positive logic including the RESET input on the XADC primitive which would be active High (1).

 

 

Ken Chapman
Principal Engineer, Xilinx UK
0 Kudos
Highlighted
Explorer
Explorer
10,333 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution

The same reset is connected to other functioning modules (also active low) in the block design, so this isn't the problem.

 

Anyway, I used the reference design and tweaked the XADC module created by the wizard to get pretty much the same parameters, i.e. :

 

XADC_INST : XADC
generic map(
INIT_40 => X"B000", -- config reg 0
INIT_41 => X"21F0", -- config reg 1
INIT_42 => X"0800", -- config reg 2
INIT_48 => X"4701", -- Sequencer channel selection
INIT_49 => X"0000", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B877", -- Temp alarm trigger
INIT_51 => X"57E4", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"B363", -- Temp alarm OT upper
INIT_54 => X"A425", -- Temp alarm reset
INIT_55 => X"52C6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"A93A", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt")

 

This made the XADC work (in the block design as well), but in a different mode than I originally intended ("channel sequencer" instead of "single channel"). I only need the temperature of the FPGA and the voltages are not important to me right now, but I can live with this solution.

0 Kudos
Explorer
Explorer
5,680 Views
Registered: ‎11-03-2013

Re: XADC module

Jump to solution

By the way, the above mentioned parameters are for the following setting in the wizard:

 

1.png

 

2.png

 

3.png

 

0 Kudos