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Adventurer
Adventurer
617 Views
Registered: ‎06-04-2010

XADC output is incorrect until I start the Vivado Hardware Manager

I'm working with an XADC and reading the most significant byte from it's output word. The resolution looks incorrect. It ranges only from 0x3A to 0x3F.  If I fire up the hardware manager however, everything works as it should. So my question is, what exactly is happening to the XADC when the XADC system monitor starts?  Because whatever it it seems to be fixing my problem...

 

Here's a video showing the issue:

https://www.youtube.com/watch?v=vxrqPcMaPY0&feature=youtu.be

 

Thanks!

-Adam

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5 Replies
Adventurer
Adventurer
560 Views
Registered: ‎06-04-2010

Re: XADC output is incorrect until I start the Vivado Hardware Manager

Bump for any assistance. Thanks!

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Moderator
Moderator
522 Views
Registered: ‎04-18-2011

Re: XADC output is incorrect until I start the Vivado Hardware Manager

Hi @ajcrm125

 

Sorry to see no one has replied... 

 

So how is your XADC set up? What mode is it in? What channel is this?

Is it external input and if so how is it set up is it a ubipolar or bipolar?

0x3F0 is only about 250mV on the unipolar scale,is there any reason why the analog input would sit there?

Is the FPGA always configured? The hw manager opening should have no impact on the XADC really.

 

Why are you reading the Most Significant Byte only?

How do you read it? Do you use the driver that comes with the XADC and print over UART?

 

cheers, 

 

Keith 

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Adventurer
Adventurer
516 Views
Registered: ‎06-04-2010

Re: XADC output is incorrect until I start the Vivado Hardware Manager

Hi Keith,

Thanks for the reply.  See comments below...

 

So how is your XADC set up?

Interface Selected: DRP

XADC operaring mode: channel_sequencer

AXI4Stream Interface: false

Timing Mode: Continuous

DCLK Freq: 24Mhz

Sequencer Mode:  Continuous

Channel Averaging: None

Enable External Mux: false

 

What mode is it in?

Channel sequencer mode

 

What channel is this?

vauxp3

 

Is it external input and if so how is it set up is it a ubipolar or bipolar?

External unipolar input. vauxn3 is tied to GND. 

 

0x3F0 is only about 250mV on the unipolar scale,is there any reason why the analog input would sit there?

Nope none that I can think of. The POT connected to the analog input is grounded when I fire up the design.

 

Is the FPGA always configured?

Yes a microcontroller on the board programs the FPGA and logic within the FPGA design reads values from the XADC and sends them over to the micro continuously via the SPI bus. 

 

The hw manager opening should have no impact on the XADC really.

When the hw manager opens up it doesn't do anything to the XADC via the XADC jtag DRP interface?

 

Why are you reading the Most Significant Byte only?

The Z80 softcore is an 8bit CPU and he's the guy that's making use of the data.

 

How do you read it?

I have a small FSM that sends read instructions through the DRP interface. 

 

Do you use the driver that comes with the XADC and print over UART?

No the terminal you saw in the video was from the microcontroller's UART. The XADC data is sent from the FPGA to the  micro and printed from there. 

 

Is there any time requirement between when reset deasserts on the XADC and when the user can start issuing read instructions?  I was messing with the FSM to add states to read initial values from the config regs and noticed that all of a sudden the issue went away.  Still experimenting but it seems if I add a delay of a few cycles between reset and DRP reads the output looks correct.  

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Moderator
Moderator
510 Views
Registered: ‎04-18-2011

Re: XADC output is incorrect until I start the Vivado Hardware Manager

Hi

I can't say for sure.
I would expect that the fsm should be waiting on eoc +the channel_out value corresponding to vaux3 before trying to read a result.

I was going to suggest taking a look at the jtag locked pin but I don't think that is the issue it seems more like you have some issue around it coming out of reset.
It's hard to say when you I'm not familiar with your design
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Moderator
Moderator
490 Views
Registered: ‎04-18-2011

Re: XADC output is incorrect until I start the Vivado Hardware Manager

What other channels are you converting in the sequence?
What is your DCLK divide?
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