03-24-2020 02:00 AM
I have been reading a datasheet for the XADC in Zynq SoC (please see the attachment). On page 63 there is statement "The XADC track/hold amplifiers return to track mode as soon as a conversrion starts. Therefore, the aquisition on the next channel can start during current conversion cycle." I am confused by this information. I thought that it is necessary to preserve the value of a sample during whole conversion time. Please can anybody explain to me how does it work? Thanks.
03-27-2020 08:43 PM
This is explained in figure below
N+1 channel is acquired when channel N is being converted , Busy will remain asserted until conversion process is in progress .
MUXADDR[4:0] here indicate the address of the next channel in a sequence to be converted, but when you look at CHANNEL output , it gives current channel number which is being converted.
03-30-2020 12:49 AM
thank you for your reaction. Does it mean that there are two memory capacitors associated to one ADC module? The first one preserves for conversion the voltage sample acquired from channel N and the second one is being charged by voltage at the channel N+1 in parallel with conversion of channel N sample?
03-30-2020 02:16 AM
This was covered on the other thread, the circuit is proprietary. you don't really need to know the details of it to use the XADC.