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Adventurer
Adventurer
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Registered: ‎03-16-2020

XADC sampling and conversion sequence

Hello,

I have been reading a datasheet for the XADC in Zynq SoC (please see the attachment). On page 63 there is statement "The XADC track/hold amplifiers return to track mode as soon as a conversrion starts. Therefore, the aquisition on the next channel can start during current conversion cycle." I am confused by this information. I thought that it is necessary to preserve the value of a sample during whole conversion time. Please can anybody explain to me how does it work? Thanks.

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @Steven 

This is explained in figure below

temp1.jpg

N+1 channel is acquired when channel N is being converted , Busy will remain asserted until conversion process is in progress .

MUXADDR[4:0] here indicate the address of the next channel in a sequence to be converted, but when you look at CHANNEL output , it gives current channel number which is being converted.

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Adventurer
Adventurer
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Registered: ‎03-16-2020

Hello pthakare,

thank you for your reaction. Does it mean that there are two memory capacitors associated to one ADC module? The first one preserves for conversion the voltage sample acquired from channel N and the second one is being charged by voltage at the channel N+1 in parallel with conversion of channel N  sample?

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Moderator
Moderator
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Registered: ‎04-18-2011

Hi @Steven 

This was covered on the other thread, the circuit is proprietary. you don't really need to know the details of it to use the XADC. 

Keith 

 

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