11-01-2018 02:22 PM
I am interfacing a Genesys 2 Board (Kintex-7 XC7K325T-2FFG900C) with an AD9681 FMC Eval Card. I've been working on modifying the design from XAPP524 but I am running into an issue with the generated "BitClk_RefClkOut". The AD eval card puts the data and frame clock signals into bank 16, while the data clock is put into bank 17. This means that when I try to implement the design for my configuration there is a BUFR that is trying to send a clock from X0Y4 to X0Y5. To make matters worse, the data clock is fed into FMC_LA17 which is a SRCC pin, therefore I cannot use a BUFMR. My thought was to take the output of the ISERDES clock and put it into a BUFG and feed that into a BUFR for X0Y4 and a BUFR for X0Y5, but it looks like this cannot be done.
Does anyone know a way to get route these clock signals in a compatible manner? Changing the pins is not an option unfortunately...
11-02-2018 07:33 AM
After doing some reading on the forums it looks like the best solution is to use an MMCM. So what I ended up implementing is:
ISERDES DCO -> MMCM -> BUFG (500 MHz)
-> BUFG (125 MHz)
While it passes DRC now, this has led to a bunch of timing failures when implementing:
When looking at the clock paths of the MMCM they're sprawled out all over the part
What is the best way to go about getting this project to meet timing?
11-02-2018 09:08 AM
I haven't seen your input constraint but I can almost guarantee that it won't close timing statically at 1Gbps.
I can tell you as you increase the data rate it is extremely difficult to close the timing statically. The difference in the min and max delay in the corners gets too far apart for it to really work statically.
As a rule of thumb, if you add the setup and hold slack and you don't get a positive number this will indicate that it wont be possible to adjust the data with an IDELAY or adjust the clock position with the MMCM to a point that is going to work across all corners
11-02-2018 12:02 PM
11-05-2018 01:00 AM
It is not a bad start point but remember that you have to understand your clock and data allignement and also you will have to implement your own bitslip since this application is for 7:1