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Visitor mikeocadi
Visitor
447 Views
Registered: ‎02-19-2019

XAPP1064 Issue when trying to implement two LVDS Rx

Hi,

Spartan6, LX9

We have a design which was using 8 LVDS data lanes and 1 clock input lane, these all come from a LVDS Tx device which can operate in either 2 x 4 lane mode or 8 lane mode.

Everything seemed to be working well. I can capture data in 4 lane and 8 lane mode.

Recently we have discoverd that in 8 lane mode there is a need to treat it as two seperate 4 lane interfaces each with their own clock, Port A, Port B. and over PVT that the clocks for port A and port B can differ by +/- 2 UI  or 2/7 of the clock rate of the datarate (data is running at 7 times the frame clock)

My issue is that all my inputs LVDS Data and Clock all enter the FPGA on Bank 0, and now using xapp1064 LVDS Rx I need to use 2 Plls in order to have two seperate LVDS Rxs.

One LVDS Rx is ok and will synthesise and Map ok. The second is causing a problem due to having to use a PLL in the lower half of the FPGA and all ISERDES are in the top bank.

I manually located the BUFPLLs to the top bank, but now the error is that there is no way for the bottom pll to connect to the bufio2 and bufio2_fb in the top bank. I applied the CLOCK_DEDICATED_ROUTE False paramter to the two buffers in the ucf to allow Map to complete.

Is there any way to make connection from the top bank bufio2 and bufio2_fb to the PLL in the lower half of the fpga ?  Or am I grasping at straws and fundamentally this will never work.

 

Capture.PNG

Xapp1064 says:- Bottom-half PLLs can be driven by top-half BUFIO2 with feedback (if required) through bottom-half BUFIO2FB

but I think this is a typo in the document ? Or is there some route or way to use clock resources to get over this issue ?

I know that if we knew before hand that the ideal solution would be to have port A all come in on bank 0 and use top pll, and have port B all come in on bank 2 and use the bottom Pll, but boards are laidout now.

Is it possible to determine the the skew between clock A and clock B (I was thinking use a fast clock and generate a count, more clock ticks = more skew) and then offset datalanes B by this ammount in the IODELAY blocks while still using Clock A as the source for the PLL and ISERDES etc. The IODELAYs are currently used by the LVDS Rx but I am wondering is it possible to manually add offset or adjustment to them

 

WARNING:Place:1112 - Unroutable Placement! A BUFIO / PLL clock component pair
have been found that are not placed at a routable BUFIO / PLL site pair. The
BUFIO component <lvds_rx_b/inst_clkin/P_clk_bufio2_inst> is placed at site
<BUFIO2_X4Y29>. The corresponding PLL component
<lvds_rx_b/inst_clkin/rx_pll_adv_inst> is placed at site <PLL_ADV_X0Y0>. The
BUFIO can use the fast path between the BUFIO and the PLL if the BUFIO is in
TOPor BOTTOM edge and both the BUFIO & PLL are placed in the same half of the
device (TOP or BOTTOM). This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<lvds_rx_b/inst_clkin/P_clk_bufio2_inst.DIVCLK> allowing your design to
continue. This constraint disables all clock placer rules related to the
specified COMP.PIN. This placement is UNROUTABLE in PAR and therefore, this
error condition should be fixed in your design.
WARNING:Place:1139 - Unroutable Placement! A BUFIOFB / PLL clock component pair
have been found that are not placed at a routable BUFIOFB / PLL site pair.
The BUFIOFB component <lvds_rx_b/inst_clkin/P_clk_bufio2fb_inst> is placed at
site <BUFIO2FB_X4Y29>. The corresponding PLL component
<lvds_rx_b/inst_clkin/rx_pll_adv_inst> is placed at site <PLL_ADV_X0Y0>. The
BUFIOFB can use the fast path between the BUFIOFB and the PLL if the BUFIOFB
is in TOPor BOTTOM edge and both the BUFIOFB & PLL are placed in the same
half of the device (TOP or BOTTOM). This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<lvds_rx_b/inst_clkin/P_clk_bufio2fb_inst.O> allowing your design to
continue. This constraint disables all clock placer rules related to the
specified COMP.PIN. This placement is UNROUTABLE in PAR and therefore, this
error condition should be fixed in your design.

 

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2 Replies
Visitor mikeocadi
Visitor
398 Views
Registered: ‎02-19-2019

Re: XAPP1064 Issue when trying to implement two LVDS Rx

Ok, I have taken the route that what I am trying to do is probably technically not feasible. i.e have a bottom located PLL drive bufio2 and bufio2_fb buffer in the top IO bank.

My plan now is to consider the two ports as individual and individially select wether I am using port A (4 lvds lanes and Clock A) or portB (4 lvds lanes and Clock B)

My plan is to use top located PLL connected to all LVDS input lanes (IODELAYS, and ISERDES) and depending on wether I want portA or PortB select either CLOCK A or CLOCK B to connect to the PLL.

ISSUE:- At the moment this is failing to either Place or route for me depending on what I have tried.

I have tried

2x IBUFGDS to mux (Which is just the addition of a second IBUFGDS to the original design and a simple Mux)

ERROR:Route:471 -
This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
routed:
Unrouteable Net:lvds_rx_a/inst_clkin/rx_clk_in

 

2x IBUFGDS to BUFGMUX

ERROR:Place:1136 - This design contains a global buffer instance,
<lvds_rx_a/inst_clkin/BUFGMUX_inst>, driving the net,
<lvds_rx_a/inst_clkin/rx_clk_in>, that is driving the following (first 30)
non-clock load pins.
< PIN: lvds_rx_a/inst_clkin/iodelay_m.IDATAIN; >
< PIN: lvds_rx_a/inst_clkin/iodelay_s.IDATAIN; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "lvds_rx_a/inst_clkin/BUFGMUX_inst.O" CLOCK_DEDICATED_ROUTE = FALSE; >

 

2x IBUFDS to mux

This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
routed:
Unrouteable Net:lvds_rx_a/inst_clkin/rx_clk_in

2x IBUFDS to BUFGMUX

ERROR:Place:1136 - This design contains a global buffer instance,
<lvds_rx_a/inst_clkin/BUFGMUX_inst>, driving the net,
<lvds_rx_a/inst_clkin/rx_clk_in>, that is driving the following (first 30)
non-clock load pins.
< PIN: lvds_rx_a/inst_clkin/iodelay_m.IDATAIN; >
< PIN: lvds_rx_a/inst_clkin/iodelay_s.IDATAIN; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "lvds_rx_a/inst_clkin/BUFGMUX_inst.O" CLOCK_DEDICATED_ROUTE = FALSE; >

 

Verilog of the Input buffers, and the two different mux types, as seen above I have tried all combinations :-

IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
iob_clk_in (
.I (clkin_p),
.IB (clkin_n),
.O (rx_clka_in));


IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
iob_clkb_in (
.I (clkinb_p),
.IB (clkinb_n),
.O (rx_clkb_in));

//BUFGMUX #(
// .CLK_SEL_TYPE("SYNC") // Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
// )
// BUFGMUX_inst (
// .O(rx_clk_in), // 1-bit output: Clock buffer output
// .I0(rx_clka_in), // 1-bit input: Clock buffer input (S=0)
// .I1(rx_clkb_in), // 1-bit input: Clock buffer input (S=1)
// .S(portSel) // 1-bit input: Clock buffer select
// );

assign rx_clk_in = portSel ? rx_clkb_in : rx_clka_in;

Anybody any ideas or can help ?

 

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Observer jon.w
Observer
247 Views
Registered: ‎12-13-2018

Re: XAPP1064 Issue when trying to implement two LVDS Rx

Hi Mike,

I'm a little slow getting to this post so apologies if you've already resolved your issues.  I don't have any direct answers, but can perhaps offer a different approach.

I haven't actually tried this, so I'm not sure if it would be successful.  When operating in two port mode, could you use the recovered clock from A, then treat the port B clock lines just as another set of data lines and use them for bitslip alignment?  This assumes that port A and B are running at the same bitrate.  So instead of using two PLLs, you'd use one to generate the 7x clock.  Of course that assumes that port A and B are running at the same bitrate.  Once you have the clock, you should be able to sample the port B clock just like a data line and use a separate bitslip state machine to align it and the associated data lines to the serdesstrobe.

Hopefully this makes some sense (and works) and you find it useful.

 

Jon

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