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Adventurer
Adventurer
202 Views
Registered: ‎08-22-2019

XC2VP20 FPGA

Hi xilinx team. I am using a board which is having vertex ll pro XC2VP20 fpga. And there is single ended 100MHz clock feeding into it. I want to divide the clock and generate 62 MHz which is a challenging task for me. I am writing a code in VHDL in which I am successfully able to divide my clock by 2,4,8,16 but if when I want to generate my clock 62 MHz I have to check my rising edge of the clock and divide my 100MHz clock by 100MHz/ 1.612 to achieve 62MHz clock, which is floating value how can I do this any idea? Please. And I am using ise design suite 10.1 version. Thanks at the earliest.
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2 Replies
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Registered: ‎06-21-2017

Re: XC2VP20 FPGA

Can you use a DCM for this?  You should not be dividing a clock in logic if you want to use the divided clock to clock any registers.

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Adventurer
Adventurer
188 Views
Registered: ‎08-22-2019

Re: XC2VP20 FPGA

Hi . Can you tell me in a little bit details. I am still a beginner please. Let me tell you in detail. 62MHz is to feed to my DAC. Ad9752. It's a 12 bit DAC which has parallel digital inputs. To generate a ramp I have to generate different speed of frequencies to all my digital pins of DAC but,let's keep this apart I just wanna know how to generate 62 MHz clock from fpga using VHDL code with 100MHz system clock. I am able to generate 50MHz clock and with this I achieved 780us of time period output from my DAC by input a pattern for my digital pins of my DAC. Thank you for replying.
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