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teraser
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Registered: ‎11-18-2010

XC6VLX365 DCI match fails

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Hello!

 

We've got several boards with several V6 chips.

Somehow on one board two of V6 don't load normally via SelectMAP.

 

After some debugging, we tried to boot from Jtag, and that two V6s also didn't load.

STATUS register shows, that DCI MATCH STATUS is 0.

 

I made bit-file with DCI match "no wait", and it loads OK (but also shows DCI MATCH STATUS = 0).

 

Can someone describe debugging guidelines for DCI? 

Everything with these two FPGAs seems ok, resistors soldered fine, right value and so on.

 

Maybe someone can describe the DCI feature itself, how it works - to try to find out why it could fail.

 

Thank you.

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teraser
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Registered: ‎11-18-2010

Workaround:

DCI match cycle = 6

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avrumw
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Registered: ‎01-23-2009

The DCI feature is quite well explained in the Virtex-6 SelectIO Resource User Guide (UG361).

 

But basically, it is adjusting the drive strength of outputs and/or the termination resistance of inputs and outputs based on calibration. The calibration is performed against the VRP and VRN resistors that must be supplied to each bank that has any DCI I/O. The VRP/VRN is either connected directly to the mutli-purpose VRP/VRN pins of the bank, or can be cascaded from an adjacent bank (in the same column) as long as the adjacent bank uses the same VCCO (and possibly the same VREF).

 

If you are having trouble with DCI, my first suggestion is to ensure that you are providing it a valid VRP/VRN - either directly or through cascading. If done through cascading (and this requires the appropriate DCI_CASCADE constraint in your UCF file) verify that you meet all the requirements for DCI cascading described in UG371 (in the section on DCI cascade).

 

Avrum

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teraser
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Registered: ‎11-18-2010

Thank you, Avrum.

 

I checked several times

1) VRP/VRN resistors value

2) FPGA VRP/VRN pin is soldered (with unsoldered resistors the pins has equal resistance on good boars and the "bad" one)

3) UCF file has constraint CONFIG DCI_CASCADE = "15 16";

 

To my current knowledge it seems ok.

 

@avrum, can you suggest any reasons for DCI match algorithm to fail? What power rails are involved in DCI matching? Any other ideas?

 

Also attaching ddr banks from scheme.

 

 

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gnarahar
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Registered: ‎07-23-2015

@teraser Can you try driving additional CCLK cycles and check what happens?  

 

Also to make sure, only this board (each board with 2 of V6 on them) has the issue while others boards with the same design work fine?

 

Can you also share the UCF file & log file after configuration. 

- Giri
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teraser
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Registered: ‎11-18-2010

@gnarahar,

 

I will add several empty words in the bit file, will it be OK?

 

Yes, we've got 10th of boards (each with 4 V6) and the issue only with one board.

 

Attaching UCF file. As soon as I will get log, I'll post it.

 

Thank you!

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gnarahar
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Registered: ‎07-23-2015

@teraser Where is your CCLK coming from? You just need to drive additional clock cycles. Check this AR https://www.xilinx.com/support/answers/42128.html

- Giri
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teraser
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Registered: ‎11-18-2010

@gnarahar, I'm loading from JTAG.

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gnarahar
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Registered: ‎07-23-2015

@teraser Ok. share the configuration log once you have it

- Giri
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teraser
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Registered: ‎11-18-2010
INFO:iMPACT - Current time: 17.11.2016 17:32:08
// * BATCH CMD : Program -p 2 
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max. Reading:   41.02 C
1: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
1: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.496 V, Max. Reading:   2.511 V
2: Device Temperature: Current Reading:   43.98 C, Min. Reading:   40.53 C, Max. Reading:   43.98 C
2: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
2: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.502 V
3: Device Temperature: Current Reading:   40.04 C, Min. Reading:   37.09 C, Max. Reading:   40.04 C
3: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
3: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.496 V, Max. Reading:   2.502 V
4: Device Temperature: Current Reading:   42.01 C, Min. Reading:   39.05 C, Max. Reading:   42.01 C
4: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
4: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.496 V, Max. Reading:   2.505 V
5: Device Temperature: Current Reading: -273.00 C, Min. Reading: -273.00 C
5: VCCINT Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
5: VCCAUX Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
'2': Programming device...
 Match_cycle = 2.
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0010 0001 0111 1000 0011 0011 1100 0000 
PROGRESS_END - End Operation.
Elapsed time =      8 sec.
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teraser
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INFO:iMPACT - Current time: 17.11.2016 17:32:54
// * BATCH CMD : Program -p 2 
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max. Reading:   41.52 C
1: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
1: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.496 V, Max. Reading:   2.511 V
2: Device Temperature: Current Reading:   43.98 C, Min. Reading:   42.99 C, Max. Reading:   44.47 C
2: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
2: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.487 V, Max. Reading:   2.508 V
3: Device Temperature: Current Reading:   40.53 C, Min. Reading:   37.09 C, Max. Reading:   40.53 C
3: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
3: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.502 V
4: Device Temperature: Current Reading:   42.50 C, Min. Reading:   39.05 C, Max. Reading:   42.50 C
4: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
4: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.505 V
5: Device Temperature: Current Reading: -273.00 C, Min. Reading: -273.00 C
5: VCCINT Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
5: VCCAUX Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
'2': Programming device...
 Match_cycle = 2.
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0010 0001 0111 1000 0011 0011 1100 0000 
PROGRESS_END - End Operation.
Elapsed time =      7 sec.

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teraser
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Registered: ‎11-18-2010

@gnarahar, I've posted twice, but it disappears. Trying once more :)

 

INFO:iMPACT - Current time: 17.11.2016 17:32:54
// * BATCH CMD : Program -p 2 
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max. Reading:   41.52 C
1: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
1: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.496 V, Max. Reading:   2.511 V
2: Device Temperature: Current Reading:   43.98 C, Min. Reading:   42.99 C, Max. Reading:   44.47 C
2: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
2: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.487 V, Max. Reading:   2.508 V
3: Device Temperature: Current Reading:   40.53 C, Min. Reading:   37.09 C, Max. Reading:   40.53 C
3: VCCINT Supply: Current Reading:   1.072 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
3: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.502 V
4: Device Temperature: Current Reading:   42.50 C, Min. Reading:   39.05 C, Max. Reading:   42.50 C
4: VCCINT Supply: Current Reading:   1.075 V, Min. Reading:   1.072 V, Max. Reading:   1.075 V
4: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.505 V
5: Device Temperature: Current Reading: -273.00 C, Min. Reading: -273.00 C
5: VCCINT Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
5: VCCAUX Supply: Current Reading:   0.000 V, Min. Reading:   0.000 V
'2': Programming device...
 Match_cycle = 2.
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0010 0001 0111 1000 0011 0011 1100 0000 
PROGRESS_END - End Operation.
Elapsed time =      7 sec.
--
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teraser
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Registered: ‎11-18-2010

@gnarahar, attaching log file.

 

Tried three times to add reply with "insert code", but post disappears...

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teraser
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Registered: ‎11-18-2010

Workaround:

DCI match cycle = 6

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gnarahar
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Registered: ‎07-23-2015

@teraser Thanks for updating the thread after the SR closure :) 

 

Please close the thread in the interest of other forum users. 

- Giri
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Don’t forget to reply, kudo, and accept as solution.
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bato990
Observer
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Registered: ‎10-09-2014

Hello

I have the same problem with Kintex UltraScale boards.

I have two boards with same design, but only one of them works with DCI enabled I/Os.

 

Boards information:

1- FPGA: xcku115-flvb2104-1-i

2- VRP of bank 45, bank 46, bank 44 and bank 53 was connected to ground with a 240 ohm pull down resistors.

 

Different tests and their result:

1- VCCO (and other powers) of each bank was measures in a possible point as close as to the FPGA.

Result: VCCOs (and other powers) were OK.

 

2- set VRP multipurpose pins as user I/O and send a clock to them.

result: All clocks  were received in the resistors connected to the VRP pins. Therefore the connection and soldering of VRP resistors are correct.

 

3- The value of resistors was measured. They are correct (240 ohm).

 

4- Same codes with DCI enabled I/Os was tested in the different boards?

result: Only one board has problem with DCI.

 

5- I wrote three different projects and in each project one of the banks was tested (bank 45, bank 46, bank 44 and bank 53 were tested).

result: None of them was worked. By this test i think the DCI problem is not related to the VRP or VCC. It is not possible that all banks under test have problems like soldering or power or the possibility of this situation is very low.

 

6- I write a project and disabled the DCI match (set it to "no-wait) and use DCIRESET primitive to reset DCI after programming. 

result: The LOCKED pin of DCIRESET  is always Zero and independent of the RST pin value in the only one board that has problem. In the other boars after reset, LOCKED pins is asserted and everything is OK.

 

I don't have any other idea and i think that problem is the FPGA or maybe PCB. 

I will give many thanks to everyone that can help me!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

 

 

 

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