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Contributor
Contributor
331 Views
Registered: ‎05-17-2018

XC7K325T HP banks power supply for LVDS

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In my system,I use 1.5V supply for HP Banks.But I will receive a 200MHz LVDS signal for my system CLK.How does this affect my design?

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Xilinx Employee
Xilinx Employee
288 Views
Registered: ‎06-06-2018

Re: XC7K325T HP banks power supply for LVDS

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Hi @chenchunqi ,

In my system,I use 1.5V supply for HP Banks.But I will receive a 200MHz LVDS signal for my system CLK.How does this affect my design?

---- I understood, You are concerned about the quality of reception or interface between 200MHz signal coming from outside and LVDS pin of FPGA.

If you are using SDR/DDR recivers with LVDS IO standard you can refer the Interface performance of LVDS (given in Mb/s). For more information refer page 13 of DS182 (v2.17).

If you are not using SDR/DDR recivers with LVDS IO standard, then you need to perform IBIS Simulation to confirm about the quality of reception (LVDS reception). For Performing IBIS Simulation Xilinx Provides IBIS Models. You can download the IBIS Models from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/kintex-series-fpgas.html or you can Generate IBIS Models from by referring this AR#50957.

 

Note : The Transmitter 200MHz Signal should be of LVDS IO Standard. And also note that LVDS is not a rail to rail voltage, you can succesfully interfaces 2 LVDS Signal with different VCCO if you meet certain conditions. For more refer this AR#43989.

 

Hope this helps .

 

Regards,

Deepak D N

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Please reply or give kudo or Accept as a Solution.

----------------------------------------------------------------------------------------------------

Regards,
Deepak D N
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2 Replies
Xilinx Employee
Xilinx Employee
289 Views
Registered: ‎06-06-2018

Re: XC7K325T HP banks power supply for LVDS

Jump to solution

Hi @chenchunqi ,

In my system,I use 1.5V supply for HP Banks.But I will receive a 200MHz LVDS signal for my system CLK.How does this affect my design?

---- I understood, You are concerned about the quality of reception or interface between 200MHz signal coming from outside and LVDS pin of FPGA.

If you are using SDR/DDR recivers with LVDS IO standard you can refer the Interface performance of LVDS (given in Mb/s). For more information refer page 13 of DS182 (v2.17).

If you are not using SDR/DDR recivers with LVDS IO standard, then you need to perform IBIS Simulation to confirm about the quality of reception (LVDS reception). For Performing IBIS Simulation Xilinx Provides IBIS Models. You can download the IBIS Models from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/kintex-series-fpgas.html or you can Generate IBIS Models from by referring this AR#50957.

 

Note : The Transmitter 200MHz Signal should be of LVDS IO Standard. And also note that LVDS is not a rail to rail voltage, you can succesfully interfaces 2 LVDS Signal with different VCCO if you meet certain conditions. For more refer this AR#43989.

 

Hope this helps .

 

Regards,

Deepak D N

----------------------------------------------------------------------------------------------------

Please reply or give kudo or Accept as a Solution.

----------------------------------------------------------------------------------------------------

Regards,
Deepak D N
---------------------------------------------------------------------------
Please Kudo and Accept as a Solution, If it helps.
---------------------------------------------------------------------------

View solution in original post

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Teacher drjohnsmith
Teacher
285 Views
Registered: ‎07-09-2009

Re: XC7K325T HP banks power supply for LVDS

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If its a clock, its easy,
just AC couple the signals through say 100 nf capacitors,
and terminate at the receiver.
gets rid of all the IO voltage problems,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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