XC7K70T driven input pins prior to configuration

[a.bezanson@dal.ca]

We have a XC7K70T in our application that is slaved to another FPGA.  During configuration of the master FPGA the pins between the other FPGA and the XC7K70T part are driven high (to 1.8V).  Does this present a risk to the XC7K70T part?

An image of the power on sequence is shown in the attached image with the configuration of the master showing a fair amount of leakage onto the XC7K70T power rails.  We have not observed any faults related to this non-ideal behavior but would like some pointers as to whether this presents a risk or how we'd retire this risk.

[alesea]

Feeding current into the device,

Is handled under the latchup spec, of <100 mA per bank, and < 200 mA for the device.

I suspect you are just fine, as Iccio for a bank is typically less than a few mA when unpowered (see quiescent current spec in data sheet).

So, no harm, but you mat see IO glitching as power is applied (power not in sequence specified is not guaranteed glitch free).