This is a complex situation and I’m still working though it, but I believe I have identified one key issue which I will try to describe in outline to start with.
The device is a Spartan 6 part XL6LX45T-3CSG324I. The tools are ISE14.7 webpack running under Windows 7 64 bit.
The FPGA works in conjunction with a general purpose 8 bit micro-controller and the FPGA logic major sub-systems are :
general purpose logic running on slower clocks mostly 50 MHz.
interface to two 14Bit 250 MSPS ADCs plus two 32K x 16 bits BRAM into which the ADCs output data is written. This logic works with a 250 MHz clock.
a PCIe interface in the form of an IP block purchased from Northwest Logic Inc.
After much work, the key problem I want to focus on is that after power-up and successful FPGA configuration as indicated by Done going high and Init staying high, all the general purpose logic and the PCIe block appear to be working but the ADC BRAM is not being written to. Some samples of the FPGA exhibit this, some do not and to further complicate matters it is FPGA startup temperature dependant – in one particular FPGA for example, if it is below around 23 deg.C. at configuration time the fault appears, if above this temperature it works OK. On some FPGAs it does not appear at all.
One practical complication is that the logic between the two ADCs inputs and the BRAM blocks is running on a 250 MHz clock which makes it very difficult to monitor anything in that area of the logic. I have now spent several weeks carrying out tests to try to eliminate possible causes of this fault, eg logic design issues, project settings, power supplies etc.
Rather than flooding you with information, my suggestion is that if you tell me what extra information you would like me to send to you I will respond.
Attached is a photo of the whole PCB and the top and bottom in the region of the FPGA.
Do you have any suggestion about what to do ? Best regards, Andrea