cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
cesargufer
Visitor
Visitor
6,912 Views
Registered: ‎11-07-2014

Xapp524 FMC Pins

Hi all

 

I am working with Zedboard for reading data from a TI ADC(AFE5807EVM), I have a FMC-DAC Adapter card between the zedboard and the ADC. I have to deserialize the data coming from ADC in LVDS serial mode.

 

I have been following the example design of XAPP52. In the documentation of this desing there is a photo of the system where I can see that uses the same ADC to FMC card that I use. 

 

 IMAG0136.png

 

I have read the documentation of FMC-DAC adapter card and I have found that Frame Clock and Bit Clock are routed to the following pins in the FMC side

 

FCLK_P G6

FCLK_N G7

DCLK_P D20

DCLK_N D21

 

adpater.png

 

 

 The example design uses a Kintex7 board so these pins are routed internally to

 

Signal          fmc-pin     FPGA-input 

========   ======   ===========

FCLK_P       G6            FMC_LPC_LA00_CC_P

FCLK_N       G7            FMC_LPC_LA00_CC_P

DCLK_P       D20          FMC_LPC_LA17_CC_P

DCLK_N       D21          FMC_LPC_LA17_CC_P

 

As it can be seen in the Kintex 7 schematics

 

Kintex_FMC.png

 

 

 

However in the XAPP52 design uses different inputs of the FMC connector, C22 and C23, for the frame clock 

 


Signal          fmc-pin     FPGA-input 

========   ======   ===========

FCLK_P       C22          FMC_LPC_LA18_CC_P

FCLK_N       C23          FMC_LPC_LA18_CC_P

DCLK_P       D20          FMC_LPC_LA17_CC_P

DCLK_N       D21          FMC_LPC_LA17_CC_P

 

 

The following lines are part of the ucf file of the design

 

NET  "FCLK_p_pin"                LOC = AD27; # FMC_LPC_LA18_CC_P   IOSTANDARD=LVCMOS25  VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_13
NET  "FCLK_n_pin"                LOC = AD28; # FMC_LPC_LA18_CC_N   IOSTANDARD=LVCMOS25  VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_13
NET  "DClk_p_pin"                LOC = AB27; # FMC_LPC_LA17_CC_P   IOSTANDARD=LVCMOS25  VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_13
NET  "DClk_n_pin"                LOC = AC27; # FMC_LPC_LA17_CC_N   IOSTANDARD=LVCMOS25  VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_13

 

Why the example design uses C22/C23 instead of G6/G7 FMC pins for frame clock? Is that correct??

 

Thanks,

 

César

 

 

 

 

 

 

 

0 Kudos
6 Replies
mcgett
Xilinx Employee
Xilinx Employee
6,899 Views
Registered: ‎01-03-2008

Your system has three boards in it:

  1)  AFE5807EVM - TI ADC Eval Module

  2) XMC-FMC Adapter card

  3) ZedBoard or KC705

 

The first schematic that you posted was from the AFE5707EVM (1) showing the connections to a Samtec ASP-127797-01 connector which is typically used for XMC applications.  The second schematic that you posted was from the KC705 (3) showing connections to the FMC LPC interface.

 

What you are missing is the information on how the XMC-FMC Adapter (2) card connections the signals between the two interfaces.  (G6/G7 on the XMC side is not connected to the G6/G7 on the FMC side.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
cesargufer
Visitor
Visitor
6,889 Views
Registered: ‎11-07-2014

Hi

 

Thank for your answer.

 

I am a bit confused about the XMC-FMC adapter card. As you said my system has three boards

 

1 . AFE5807evm

2.  ADC to FMC adapter card. (NOT XMC-FMC Adapter card)

3 . Zedboard(my design) or KC075(Xilinx application note)

 

So where is the XMC-FMC adapter? Is the same as ADC to FMC?

 

The first schematic that I posted was from ADC to FMC adapter not from the AFE5807EVM

 

http://www.ti.com/tool/fmc-adc-adapter

 

I attached this schematic with the answer

 

fmc_adc_adapter.png

 

 

Thanks

 

César

 

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
6,881 Views
Registered: ‎01-03-2008

> So where is the XMC-FMC adapter? Is the same as ADC to FMC?

 

I made a mistake.  The first page that was returned for the ASP-127797-01 connector had XMC at the top, but the connectors for XMC were a different part number.  Down further on the page the ASP-127797-01 is listed as a FMC MC-LPC-10L (Mezzanine Card, Low Pin Count, 10mm high, Leaded).  This part number was unfamiliar to me as we only use ROHS compliant parts with our boards.

 

XAPP524 does not explicitly call out any specific ADC board(s), so the I/O constraints should be treated as generic.  You need to modify them to match your system.

 

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
cesargufer
Visitor
Visitor
6,872 Views
Registered: ‎11-07-2014

Hi mgcett

 

Thank you again for your fast answer

 

You're right xapp524 does not specify any board, I mean the reference design of this application note. In the documentation folder of the reference design there is an image of the system in wich I saw the same ADC to FMC adapater card that I use. This image is the one I posted in my question.

 

 

PHOTO OF THE REFERENCE DESING XAPP524

 

IMAG0136.png

 

 

So my question is about the reference design. I think that if the design is for the system of photo, then this deign might be erroneous

 

I undestand that I need to adapt the solution to my system, but I think that in case Bit_Clock and Frame_Clock come from different IOBANKs (situation that happens with the ADC to FMC adapter) the proposal of the xapp524 might be not possible.

 

Thanks again

 

César

 

0 Kudos
mcgett
Xilinx Employee
Xilinx Employee
6,857 Views
Registered: ‎01-03-2008

When I reviewed the ZIP file earlier today, I saw the photo, but there is no mentioned of this in any of the other files that I could find.  I don't know why the photos are there.

 

Use the correct pin definitions that match your board and see if your design works. 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
esakki@babu
Adventurer
Adventurer
548 Views
Registered: ‎11-09-2018

how to do deserialize from AFE5809? I interface AFE5809 with kintex kc705 through FMC-ADC samtec connector.

I reffered xapp524 in reference design the given constraint why user sma clock is assigned for Sys_clk_p_pin and Sys_clk_n_pin?

the differential clock is given to mmcm. for 2 channel why data_0_p_pin   to data_3_p_pin 4 input data assigned?

0 Kudos