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IP2020
Visitor
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Registered: ‎01-20-2021

Xilinx FPGA LVDS interface with AC coupling/DC biasing termination related question

We have a question related to LVDS signal interface with Xilinx FPGA – Zync 7000 SoCC (XA7Z030-1FBV484Q).  

Our question is – the LVDS signal from our comparator (LMH7324) output will have a common mode of 3.7V instead of standard 1.2V due to power supply scheme (VCCO : 5V). So we would like to use one of the termination schemes from TI Application note to AC couple the signal and add DC bias as shown below. Although this brings the common mode to ~1.2V, the positive and negative LVDS signals are skewed (also shown below).

So, we would like to know if the FPGA (XA7Z030-1FBV484Q) will accept this as a valid LVDS signal? 

 

Term.jpg

 

Sch.png

(Yellow probe: Positive LVDS Signal, Green Probe: Negative LVDS Signal, Brown Probe: Input signal to the comparator)

Waveform.png

 

 

We have also tried the termination scheme that is mentioned on Pg 93 of the Xilinx FPGA datasheet (link below), however that termination scheme also gives us the same skewed output as mentioned above. So we would like to confirm if the Xilinx FPGA can accept the skewed waveform as a valid LVDS signal?

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

Termination from Xilinx datasheet - Pg93Termination from Xilinx datasheet - Pg93

Wave2.jpg

 

 

Please advise.

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Registered: ‎01-22-2015

@IP2020 

Welcome to the Forum!

Some things to consider:

  1. The Xilinx IOSTANDARD called LVDS can be received in HP banks of the XA7Z030
  2. The Xilinx IOSTANDARD called LVDS_25 can be received in HR banks of the XA7Z030
  3. See AR#43989 for a nice decision tree on using LVDS and LVDS_25
  4. The AC coupling methods you describe are suitable for clocks - and are generally NOT suitable for data
  5. Tables 2, 14, 15 in the datasheet, DS191, for the XA7Z030 give the LVDS and LVDS_25 specifications you need.
    1. Table 2 says the voltage input, VIN, on a PL-pin of the FPGA must not exceed the range -0.2V to VCCO+0.2
    2. Tables 14 and 15 say the VIDIFF range is 0.100V to 0.600V
    3. Tables 14 and 15 say the VICM range is 0.300V to 1.500V(1.425V)

In your last plot of waveforms, I see (roughly):

  • VIDIFF = 1.65 - 0.85 = 0.80V
  • VICM = (1.65 + 0.85) / 2 = 1.25V

So, your waveforms meet the VICM specification for LVDS/LVDS_25 but they do not meet the VIDIFF specification.

Cheers,
Mark

 

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IP2020
Visitor
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Registered: ‎01-20-2021

Thanks for pointing this out. 

I am curious on why the AC coupling methods that I described are suitable for clocks but not for data?

 

Thanks

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Registered: ‎01-22-2015

The AC coupling cannot pass a constant (DC) value.  So, long strings of 0 or 1 in a data stream are a problem.  However, there are coding methods (eg. Manchester) for data that ensure no long strings of 0 or 1 and allow the data to be sent through AC coupled connections.