01-20-2021 04:17 PM - edited 01-20-2021 04:26 PM
We have a question related to LVDS signal interface with Xilinx FPGA – Zync 7000 SoCC (XA7Z030-1FBV484Q).
Our question is – the LVDS signal from our comparator (LMH7324) output will have a common mode of 3.7V instead of standard 1.2V due to power supply scheme (VCCO : 5V). So we would like to use one of the termination schemes from TI Application note to AC couple the signal and add DC bias as shown below. Although this brings the common mode to ~1.2V, the positive and negative LVDS signals are skewed (also shown below).
So, we would like to know if the FPGA (XA7Z030-1FBV484Q) will accept this as a valid LVDS signal?
(Yellow probe: Positive LVDS Signal, Green Probe: Negative LVDS Signal, Brown Probe: Input signal to the comparator)
We have also tried the termination scheme that is mentioned on Pg 93 of the Xilinx FPGA datasheet (link below), however that termination scheme also gives us the same skewed output as mentioned above. So we would like to confirm if the Xilinx FPGA can accept the skewed waveform as a valid LVDS signal?
01-20-2021 05:38 PM - edited 01-20-2021 05:43 PM
Welcome to the Forum!
Some things to consider:
In your last plot of waveforms, I see (roughly):
So, your waveforms meet the VICM specification for LVDS/LVDS_25 but they do not meet the VIDIFF specification.
01-21-2021 10:02 AM
The AC coupling cannot pass a constant (DC) value. So, long strings of 0 or 1 in a data stream are a problem. However, there are coding methods (eg. Manchester) for data that ensure no long strings of 0 or 1 and allow the data to be sent through AC coupled connections.