02-20-2019 11:29 PM
I'm migrating a design compiled for spartan-6 devices (ISE based) to Artix 7 (Vivado based).
There are couple of Xilinx Primitives like LUT1,LUT4,FD,SRL16,PLL_BASE & BUFG used in the spartan-6 design. I was able to compile this design successfully in vivado for Artix 7 FPGA. But, I have concerns about its working.
1) Are the xilinx primitive functions in spartan-6 and Artix-7 same?
2) Will there be any functional issues if I use the same spantan-6 primitives like LUT1,LUT4,SRL16,PLL_BASE in Artix 7 design?
02-25-2019 01:54 PM
Hi @vinay_shenoy ,
Please take a look at the document 7 Series FPGAs Migration Methodology Guide - UG429, which shows all the compatible and not compatible primitives between the 6-series and 7-Series devices.
looking at page 19, it appears that LUT1, LUT4, and SRL16 are compatible. About the PLL, you might need to change it to PLLE2_BASE.
02-25-2019 05:37 PM
It is unusual to manually instantiate low-level primitives (like FD, LUT1, LUT4) in your HDL. It is often better to replace the primitives with pure HDL – because this will: