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Newbie
Newbie
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Registered: ‎05-30-2018

Xilinx Virtex 5 timing issue with 400MHz external crystal oscillator

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Is there any timing issue with 400MHz external crystal oscillator for Xilinx Virtex 5 XC5VLX50-100 part?

 

I've checked Virtex-5 FPGA Data Sheet (https://www.xilinx.com/support/documentation/data_sheets/ds202.pdf) and still need some clarification. I heard one engineer said "timing issue within Virtex 5 XC5VLX50-100 fpga that may cause the clock not to work at 400mhz".

 

Is it the case, even 400MHz external crystal oscillator, Virtex 5 still has timing issue with simple designs?

 

Thanks,

JH

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Newbie
Newbie
2,168 Views
Registered: ‎05-30-2018

Avrum,

 

Thank you so much for the detailed explanation. We have both  -2 and -3 speed grades parts. What we're trying to do is to create one simple free-running counter with 2.5ns time resolution, based on external 400MHz crystal oscillator. Based on the counter values, we will then be able to know how much time has elapsed during two time intervals.

 

We reworked on our existing hardware that has 320MHz crystal stuffed and replaced it with 400MHz part for finer time resolution need. We then bring this CLK in and use it on a BUFIO. So when we acquire data, we'll have the corresponding timestamp counter value recorded.

 

Thanks for your the following comment that added more confidence in our design:

"Technically the BUFIO and the input of the PLL have no problem with 400MHz clocks. The BUFG is also OK, but it is getting really close to the maximum in some devices in a -1 speed grade." 

 

 

JH

 

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Guide
Guide
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Registered: ‎01-23-2009

First, I don't know what a -100 speed grade is; the Virtex-5 came in -1 -2 and -3 speed grades.

 

Second, your question is way too broad. What do you want to do with this 400MHz clock?

  - just bring it in and use it on a BUFG

  - Just bring it in and use it on a BUFIO

  - use it as the input clock of a DCM

     - if so, in what mode

     - what do you want as the output frequencies

  -  use it as the input clock of a PLL

 

Each of these has a different answer.

 

In general, trying to run a Virtex-5 fabric at 400MHz is extremely challenging - regardless of where the clock comes from. While it is technically possible to design logic that runs at this speed, you will be limited to one or two levels of LUT at the most with extremely good routing. In a -1 device, I doubt even that is possible...

 

Technically the BUFIO and the input of the PLL have no problem with 400MHz clocks. The BUFG is also OK, but it is getting really close to the maximum in some devices in a -1 speed grade.

 

The DCM will only accept a CLKIN at this frequency in certain modes and in certain speed grades. If the DCM is not in "High Frequency Mode" then this clock is too fast in all speed grades. Even in "High Frequency Mode", 400MHz is too fast for a -1 or -2 part doing Dynamic Frequency Synthesis (i.e. using the CLKFX output), and just barely in range for a -3 device.

 

Avrum

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Newbie
Newbie
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Registered: ‎05-30-2018

Avrum,

 

Thank you so much for the detailed explanation. We have both  -2 and -3 speed grades parts. What we're trying to do is to create one simple free-running counter with 2.5ns time resolution, based on external 400MHz crystal oscillator. Based on the counter values, we will then be able to know how much time has elapsed during two time intervals.

 

We reworked on our existing hardware that has 320MHz crystal stuffed and replaced it with 400MHz part for finer time resolution need. We then bring this CLK in and use it on a BUFIO. So when we acquire data, we'll have the corresponding timestamp counter value recorded.

 

Thanks for your the following comment that added more confidence in our design:

"Technically the BUFIO and the input of the PLL have no problem with 400MHz clocks. The BUFG is also OK, but it is getting really close to the maximum in some devices in a -1 speed grade." 

 

 

JH

 

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Scholar
Scholar
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Registered: ‎09-16-2009

Don't just take Avrum's word for it - go to the source:

https://www.xilinx.com/support/documentation/data_sheets/ds202.pdf

 

All the specs he mentioned are readily available there.  I'd strongly suggest designing to those specs, and not just relying a few bench tests and the words found in a web forum... (Not trying to shoot down Avrum's response at all in that statement...)

 

Then run the proper timing analysis tools (trce) to confirm your specific design.

 

Regards,

 

Mark

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Newbie
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Registered: ‎05-30-2018

Mark,

 

Thank you for the pointer & direction.

We'll definitely do timing analysis to confirm our deign has no timing violation.

 

JH

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Guide
Guide
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Registered: ‎01-23-2009

Are the intervals you are trying to measure coming directly from a pin of the FPGA?

 

If so, you can get far finer than 2.5ns resolution. At very least you can use the IDDR to take two samples per clock, giving you 1.25ns resolution.

 

You can even go further than this and use the ISERDES. The maximum rate of the BUFIO is 644MHz or 710MHz depending on your speed grade. You can still use an ISERDES in DDR mode. Even at (say) 640MHz DDR (that's a resolution of 781ps), you can use the IDDR in 6:1 deserialize to get down to 8 samples at 160MHz or even lower if you want to use the master/slave pair of ISERDES.

 

And, yes, all the numbers I quoted came from DS202 (I should have mentioned that - thanks Mark!)

 

Avrum

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