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Visitor
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Registered: ‎12-01-2019

Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

FPGA informaion:Xilinx Zynq-7000 xc7z015clg485

I need to output the bufg CLK to fpga pin.
 
The route of the CLK OUTPUT is  clkin--->PLLE2_BASE--->bufg--->(ODDR2 add or not ) --->OBUF(LVCOMS3V3).
 
But there is a bias voltage in the output clk. How should I do? Thanks.

ODDR2 add or not does not infect the bias volatge. 
 

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Community Manager
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Registered: ‎08-08-2007

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

Hi @linazhang 

What IOSTANDARD are you using? What voltage is the bank powered at? 

Can you share a scope shot of the bias you are seeing?

 

 

Thanks,
Sandy

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Registered: ‎12-01-2019

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

thanks for your reply.

The IOSTANDARD  of output pin is lvcmos 3v3.

For the same pin  ,when the bufg clkout to pin , the bias volatge may be 1.5v.(fig1)

fig1:

bias.PNG

Once use the bufg clk division clock output to pin , there is a standard 3.3v volage level.

frequence.PNG

 

 

 

 

 

 

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

What frequency is the clock?

I can't see very well from the pictures. 

Are you saying slowing the clock down by dividing the clock makes it look better?

Another thing to think about is that normally the scope has a coupling setting. DC coupled to ground with 50ohms etc maybe this is having an effect but its more likely the frequency of the clock you are sending out.. 

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Moderator
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Registered: ‎04-18-2011

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

OK, so @250Mhz the driver is not able to drive the line all the way low or all the way high before the clock toggles again. 

So this is probably too high a frequency to be trying with a single ended IO. 

You can see when you divide it the driver is able to drive the load low and high with no issues. 

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Visitor
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Registered: ‎12-01-2019

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

Thanks for your reply.

YES, fig1  is  the clock with a bias. fig2 is the same pin ,but is a standard lvcmos 3.3v.

the different is the source of the output.

Fig1, bufg clock directly output to pin (whether through ODDR or not.)

Fig 2  the division net of bufg clock of output to pin.

So, I think I has nothing to do with the external DC couple.

 

 

 

 

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Registered: ‎12-01-2019

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

Thanks for your reply.

YES, I can redo to change the parameter of pll, reduce the frequence of bufg clock output .

 

 

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Registered: ‎12-01-2019

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

thanks for your reply.

The following test has been done:

1) 125m bufg directly output to fpga pin.  3v3 lvcmos OK

2) 208m bufg directly output to fpga pin.   has a bias .

3) 250M bufg clk , generates a divider clock 125m output to fpga pin ,3v3 lvcmos OK

3) 500M bufg clk , generates a divider clock 250m output to fpga pin , has a bias .

SO ,can I draw a conlusion that ,for a single ended IO the  frequency should not exceed 125M?

 

 

 

 

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Moderator
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Registered: ‎04-18-2011

Re: Xilinx Zynq-7000 bufg clkout to pin has a bias voltage

To be clear it is not a bias. the driver cannot drive all the way to ground or all the way to VCC because it is being driven to switch before that can happen. 

At some point you are going to have a frequency where you can't get the output logic levels. 

 

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