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Visitor agorur
Visitor
7,157 Views
Registered: ‎09-09-2015

ZC706 GTX QUAD111 SFP use Si5324 as clock

Hi all,

I am uzing two ZC706 boards and am trying to use the optical SFP connector to transmit data between them using the Aurora 64b66b block in Vivado (2015.2) in full duplex mode. I have the example project working with the same external clock connected to the SMA_MGT_REFCLK_P/N pins on both boards, however I am now tryng to integrate the design into a larger one where my clock requirements are different. I need to use the Si5324 chip for the input GTX clock and am slightly confused.

 

This design below (for the KC-705 eval board) shows the RXOUTCLK feeding into an ODDR and then into the Si5324 as the reference clock. I would do this, but it looks like the Aurora IP block doesnt have a RXOUTCLK pin, so I assume I would be using the gt_refclk1_out pin.si5324_example.jpg

 

Also, from the schematic here: http://www.xilinx.com/support/documentation/boards_and_kits/zynq-7000/zc706-schematic-xtp215-rev1-1.pdf on page 43, Si5324 accepts a differential clock input as a reference clock, and all the clock outputs of the Aurora block are single ended. Can I just tie the other input of the differential input clock to zero? 

 

Last question, I believe that the si5324 clock correction is necessary to have the least clock offset between my two zc706 eval boards, otherwise I would just feed the GT ref clk input with a free running clock from the si5324 without any feedback from the aurora block, is that correct? 

 

Thanks very much!

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Xilinx Employee
Xilinx Employee
7,148 Views
Registered: ‎08-01-2008

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

check this design 

 

XAPP1228 -  Demonstration of a 16 Lane 10G Aurora 64B/66B Link on VC7203 Application Note ( ver1.0, 8309 KB ) [PDF]

This application note explains the steps required to validate the Xilinx® LogiCORE™ IP Aurora 64B/66B IP core working at 10.3125 Gb/s serial line rate and configured as a 16-lane link on the Virtex®-7 FPGA VC7203 Characterization Kit.
Thanks and Regards
Balkrishan
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Visitor agorur
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7,133 Views
Registered: ‎09-09-2015

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

Thanks,

 

That helps some, but I am still unsure about the connections I have to make. From this forum post: https://forums.xilinx.com/t5/7-Series-FPGAs/MGT-clocking/td-p/516527, it says:

"You will need to connect the RECCLK from GT to which the design is targeted to the REC_CLOCK_P and REC_CLOCK_N pins. The synthesizer is set for pass through mode so the output clock is same as the RECCLK output from GT. To get RECCLK out from FPGA, you need to use ODDR block." 

 

It makes it sound like clock recovery is necessary, but the example design you sent me does not. I really just want to know what outputs from the Aurora block need to be connected to the rec_clock_p/n ports of the Si5324. Also, from this forum post: https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/VC707-stm1-clk-via-Si570-through-Si5324-PPM-spec/td-p/647852, it says: 

"You only need to use the Si5324 in free run mode with the 114.285 MHz crystal to generate the initial 155.52 MHz for the GTHs to operate, lock and generate a recovered clock from the received data.  See page 73, section 6.5 of the Si53xxReferenceManual for more information on the free run mode. 

 

Once you have the GTH locked to the incoming data stream, the RXRECCLK can then be driven from the FPGA to the Si5324 using the REC_CLOCK_C_P|N pins and it will switch over and locked to the clock providing a 0 PPM offset."

 

I generally understand that I need an output clock from the Aurora module to be connected back into the Rec_clk pins of the si5324, I am just not sure which pins from the aurora module need to be connected.

 

Thanks!

 

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Moderator
Moderator
7,123 Views
Registered: ‎02-16-2010

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

Do you need this custom clocking only when you use ZC706?

Aurora IP does not provide RXRECCLK as output. You will need to edit the core to get it to the top level of the IP. You can find this clock in <component_name>_wrapper.v file.
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Visitor agorur
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7,121 Views
Registered: ‎09-09-2015

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

Yes, the clocking is for when the aurora block is used within a larger system on the zc706 that won't have an external clock available (otherwise I would just input the clock from the MGT SMA pins). I will output rexrecclk then, thank you. 

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Visitor agorur
Visitor
7,118 Views
Registered: ‎09-09-2015

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

Though just to make sure, when using the sfp connectors between two boards with different clocks, using the rxrecclk is required? 

Thanks again!

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Visitor agorur
Visitor
7,113 Views
Registered: ‎09-09-2015

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

I found this old forum post about aurora on another device: https://forums.xilinx.com/t5/Connectivity/Aurora-problem-when-using-CDR-recovered-clock/td-p/67229

 

The last post states: " Really, Aurora isn't designed to be run with the recovered clock and as long as your traces are within reasonable bounds, channel bonding will take care of any channel skew and adjusting the clocking shouldn't be necessary. "

 

There's some conflicting information on this, I'd appreciate if anyone could let me know. Thanks!

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Moderator
Moderator
7,099 Views
Registered: ‎02-16-2010

Re: ZC706 GTX QUAD111 SFP use Si5324 as clock

Si5324 is used as jitter cleaning PLL. So you are not actually running the GT using recovered clock but using a cleaner clock with the help of Si5324.
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