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Contributor
Contributor
1,177 Views
Registered: ‎08-01-2017

ZYNQ DMA and AXI stream IP.

Hello

 

I'm beginner about FPGA & HDL. 

so, I try to transfer the data in ddr using AXI DMA and custom stream IP.

already I make a few custom AXI stream IP, but all of them is not work.

 

My project sequence is that reading PWM parameter from DDR and using the parameter make PWM signal(7.5kHz)

pwm_0 works well if only the parameters are entered well.

I can not be sure that the axi_stream_read_IP works well. 

I tried to assert tready every 7.5kHz and send the input stream data to the output. Although it seemed to work well in the simulation, it did not actually work. In sdk, 1word data was transmitted s_axis_mm2s, but nothing happened.

 

I lost my direction. I do not know what went wrong.

Please anyone help me.

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2 Replies
Scholar dpaul24
Scholar
1,166 Views
Registered: ‎08-07-2014

Re: ZYNQ DMA and AXI stream IP.

already I make a few custom AXI stream IP, but all of them is not work.

 

I did not completely understand the meaning of this sentence. Which IP in the given BD below is a custom AXIS IP? Did you mean to say they are not functioning properly?

 

In the case you have shown below, it is very common to verify the AXIS FIFO inputs and outputs so that you can ascertain that proper data is written and then read out. Try debugging this part.

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Explorer
Explorer
905 Views
Registered: ‎01-13-2018

Re: ZYNQ DMA and AXI stream IP.

any more update in this post ? Is there any other post which is now active for AXI DMA and AXI Stream IP ? 

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