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Registered: ‎06-15-2021

Zmod ADC1410 timing constraints problem

I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I couldn't make it to properly work.

Recently I've discovered, in this vivado repository constraint file, from line 66 to 72, that some timing constraints were missing, so I've added them into my design. Unfortunately, one of them is giving me a synthesis error.

I'm posting the specific timing constraint that's giving me problems, and so the resulting error:


create_generated_clock -name o_adc_clock_in_p -source [get_pins top/u_ZmodADC1410_Controller_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports o_adc_clock_in_p]
[Vivado 12-508] No pins matched 'top/u_ZmodADC1410_Controller_0/U0/InstADC_ClkODDR/C'.


My top level design is "top" (top.v) and my Zmod ADC controller instance is "u_ZmodADC1410_Controller_0" (ZmodADC1410_Controller_0 Core) (the first one instantiates directly the second one).
It seems it's a path problem, so, following this, I've tried the next different paths:

-source [get_pins top/u_ZmodADC1410_Controller_0/U0/InstADC_ClkODDR/C]
-source [get_pins -filter {name=~ *InstADC_ClkODDR/C}] 
-source [get_pins -hier InstADC_ClkODDR/C]

All of them, with the same error message.

If I dig into the controller files, I can see 'C' pin in its expected location (that is, in 'InstADC_ClkODDR') and in the synthesized schematic.

Lastly, I'm also posting the ADC-related constraing from my design:


set_property -dict { PACKAGE_PIN N20  IOSTANDARD DIFF_SSTL18_I } [get_ports { o_adc_clock_in_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
set_property -dict { PACKAGE_PIN N19  IOSTANDARD DIFF_SSTL18_I } [get_ports { o_adc_clock_in_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
set_property -dict { PACKAGE_PIN T17  IOSTANDARD LVCMOS18 } [get_ports { o_ch1_coupling_l }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
set_property -dict { PACKAGE_PIN T16  IOSTANDARD LVCMOS18 } [get_ports { o_ch1_coupling_h }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
set_property -dict { PACKAGE_PIN T19  IOSTANDARD LVCMOS18 } [get_ports { o_ch2_coupling_l }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
set_property -dict { PACKAGE_PIN R19  IOSTANDARD LVCMOS18 } [get_ports { o_ch2_coupling_h }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
set_property -dict { PACKAGE_PIN T18  IOSTANDARD LVCMOS18 } [get_ports { o_adc_sclk }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
set_property -dict { PACKAGE_PIN R18  IOSTANDARD LVCMOS18 } [get_ports { io_adc_sdio }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
set_property -dict { PACKAGE_PIN P18  IOSTANDARD LVCMOS18 } [get_ports { o_ch2_gain_l }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
set_property -dict { PACKAGE_PIN P17  IOSTANDARD LVCMOS18 } [get_ports { o_ch2_gain_h }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
set_property -dict { PACKAGE_PIN R16  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_2 }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
set_property -dict { PACKAGE_PIN P16  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_9 }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
set_property -dict { PACKAGE_PIN P15  IOSTANDARD LVCMOS18 } [get_ports { o_ch1_gain_l }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
set_property -dict { PACKAGE_PIN N15  IOSTANDARD LVCMOS18 } [get_ports { o_ch1_gain_h }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
set_property -dict { PACKAGE_PIN K18  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_4 }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
set_property -dict { PACKAGE_PIN J18  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_3 }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
set_property -dict { PACKAGE_PIN K21  IOSTANDARD LVCMOS18 } [get_ports { o_adc_relay_com_l }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
set_property -dict { PACKAGE_PIN J20  IOSTANDARD LVCMOS18 } [get_ports { o_adc_relay_com_h }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS18 } [get_ports { o_adc_dco_clock_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
set_property -dict { PACKAGE_PIN M19  IOSTANDARD LVCMOS18 } [get_ports { i_adc_dco_clock_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
set_property -dict { PACKAGE_PIN L19  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_5 }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
set_property -dict { PACKAGE_PIN K20  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_8 }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
set_property -dict { PACKAGE_PIN L18  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_6 }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
set_property -dict { PACKAGE_PIN K19  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_10 }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
set_property -dict { PACKAGE_PIN L22  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_7 }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
set_property -dict { PACKAGE_PIN J22  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_11 }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
set_property -dict { PACKAGE_PIN L21  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_1 }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
set_property -dict { PACKAGE_PIN J21  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_12 }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
set_property -dict { PACKAGE_PIN N22  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_0 }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
set_property -dict { PACKAGE_PIN P22  IOSTANDARD LVCMOS18 } [get_ports { i_adc_data_13 }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
set_property -dict { PACKAGE_PIN M21  IOSTANDARD LVCMOS18 } [get_ports { o_adc_cs }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
set_property -dict { PACKAGE_PIN M22  IOSTANDARD LVCMOS18 } [get_ports { o_adc_sync }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]

set_property DRIVE 4 [get_ports io_adc_sdio]
set_property DRIVE 4 [get_ports o_adc_cs]
set_property DRIVE 4 [get_ports o_adc_sclk]
set_property DRIVE 4 [get_ports o_adc_sync]

set_property SLEW SLOW [get_ports o_adc_sync]
set_property SLEW SLOW [get_ports -filter { name =~ o_adc_clock_in_* }]

create_clock -period 10.000 -name i_adc_dco_clock_p -waveform {0.000 5.000} [get_ports i_adc_dco_clock_p]

create_generated_clock -name o_adc_clock_in_p -source [get_pins -hier InstADC_ClkODDR/C] -divide_by 1 [get_ports o_adc_clock_in_p]

set_input_delay -clock [get_clocks i_adc_dco_clock_p] -clock_fall -min -add_delay 3.240 [get_ports {i_adc_data_*}]
set_input_delay -clock [get_clocks i_adc_dco_clock_p] -clock_fall -max -add_delay 5.440 [get_ports {i_adc_data_*}]
set_input_delay -clock [get_clocks i_adc_dco_clock_p] -min -add_delay 3.240 [get_ports {i_adc_data_*}]
set_input_delay -clock [get_clocks i_adc_dco_clock_p] -max -add_delay 5.440 [get_ports {i_adc_data_*}]


Any ideas in how to resolve this error? I'm pretty new in this timing-related constraints.

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