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lionrouge
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Registered: ‎01-27-2014

Zynq-7000 PL Vref pins

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Hi !
It's unclear from the docs what should I do to VREF pins.
We use Zynq-7035, FFG900 package with a SO-DIMM DDR3 memory on banks 33,34,35 (automatic MIG layout).
So, let me ask several questions:
1) Is it OK that MIG used IO_L19N_T3_VREF_34 for ddr3_ck_n[0] signal? Internal Vref was off in MIG configuration.
2) What should we do with the rest VREF pins on banks 33,34,35 to make proper external Vref?

Thanks.

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lionrouge
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Registered: ‎01-27-2014
I manually altered automatic MIG layout (it placed one of ck pins to Vref and I replaced all ck pins to another byte group - they are required to be on the same byte group). So now all Vref pins in MIG banks (33-35 in my case) are free and I will use them as Vref.
P.S. ZC706 board also have all Vref used as Vref and not IO on MIG banks.

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tenzinc
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Registered: ‎09-18-2014

Lionrouge,

 

VREF is only needed for inputs. If all the IOs on the bank outputs(ie output clocks or addresses) the then the VREF pin is free to be used as a free IO as long is not another VREF based input. If you have VREF based inputs in your bank and MIG Still uses the VREF pin freely for another IO then make sure you are using the latest Vivado and MIG versions. Make sure in the IO planner that for banks where Vref is needed that they are not used for regular IOs. 

 

 

Regards,

T



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lionrouge
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We use Vivado 2015.2. Is it late enough?
My problem is I don't know on which banks I need Vref - how to find it out?. Couldn't find it in the docs ( UG586, UG585, UG933 ).

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tenzinc
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Registered: ‎09-18-2014

Lionrouge,

 

Look in your Zynq device's datasheet. The IOSTANDARDs that need Vref should be referenced to it for their input specs. UG471 Table 1-55 also mentions which types of IOSTANDARDs require Vref or VCCO. 

 

Regards,

T

 

 



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

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lionrouge
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Registered: ‎01-27-2014
I mean I can't understand where I need Vref on MIG DDR3 SO-DIMM banks.
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lionrouge
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Registered: ‎01-27-2014
I manually altered automatic MIG layout (it placed one of ck pins to Vref and I replaced all ck pins to another byte group - they are required to be on the same byte group). So now all Vref pins in MIG banks (33-35 in my case) are free and I will use them as Vref.
P.S. ZC706 board also have all Vref used as Vref and not IO on MIG banks.

View solution in original post

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