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stevemmn
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Registered: ‎04-04-2018

Zynq 7000 Processing System FCLKCLK outputs

The FCLKCLK0-FCLKCLK3 clock outputs in the Zynq 7000 are derived from PLLs in the PS. But there is no PLL lock output to indicate they are stable. The associated FCLKRESETN signals seem to be software programmable resets and the Technical Reference Manual does not specify if the PLL lock of the associated clock keeps them asserted until the PLL has locked.

 

Is there any way to know if the PLL has locked on FCLKCLK0-FCLKCLK3 clock outputs and they are producing a valid clock signal? Or are they kept low until the PLL has locked? I was asking because I need to use one of the FCLKCLK clock outputs to drive the SEM Controller and the User Guide states that the clock to the SEM Controller must never violate the minimum period at any time. There is no reset input to the SEM Controller so it will begin operating at the first rising edge of the clock.

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watari
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Registered: ‎06-16-2013

Hi @stevemmn

 

If you only know lock signal without stability, I suggest to use RESET IP to get like lock signal.

Would you try it ?

 

Best regards,

 

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stevemmn
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Registered: ‎04-04-2018

Hi, the Zynq FCLKCLK clocks do not have a PLL lock output and the SEM Controller IP does not have a reset input.

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