05-20-2019 12:33 PM
I am having an issue with a Zynq Z-7020 pulsing its PL I/O outputs high (up to the level of the 3.3V I/O rail) on power off.
The board I am using has a voltage monitoring IC and assert its reset line low whenever the 1.0V rail drops below ~0.9V or if the 3.3V rail drops below ~2.9V. This reset line is tied to the PS_POR_B signal for the Zynq. Looking at the waveform timing, the PS_POR_B asserts quickly after the 3.3V voltage rail starts to ramp down on power off. The 1.0V rail falls down quickly after the reset line goes low. But the 3.3V rail that we are supplying to the board for all of its power (that is routed straight to their I/O banks) takes longer to bleed off because of bulk capacitance. About 50-100 ms after the 1.0V rail goes down and the 3.3V rail is still around 800-900 mV, the I/O on the PL side pulse high for 50-100 ms. The attached picture is a waveform capture of the 3.3V rail, the PL output, the 1.0V rail, and the PS_POR_B signal.
What would cause this erratic behavior?
We have helped mitigate this issue by putting a burn down resistor on the 3.3V rail that makes it ramp down quickly on power off. But I still am not sure of what caused that condition on only some of the boards.
05-20-2019 01:57 PM
I don't know if it is a good idea to monitor PS_PORB. What can it tell you about the state of the PL? Is the core supply for the PL and PS VCCINT shared?
Do you know that turning off the VCCINT 1V rail before the VCCO rails does not follow the recommended power off sequence? so we can't fully guarantee that you won't see anything funny with the IO.
You said this is normally an output pin or could something on the board drive it? once VCCINT is gone It would not be expected that anything can force an output to drive high.
It also kind of reminds me of this.
But this was a phenomenon associated with Power On rather than Power Off.
05-21-2019 05:51 AM
The PS is supplying the clock to the logic on the PL, so whenever the PS goes into reset I would expect the logic to halt. The same 1.0V powers the VCCINT for the PS and PL.
Yes, but this is a already designed all-in-one module that controls its powerup/powerdown. We just provide the module with 3.3V for all of its power. That is what I was afraid of, that Xilinx wouldn't be able to do anything because it isn't being powered down in the correct manner. That is why I just tried to consume the energy faster with a resistor to ground to reduce the amount of time the 3.3V rail took to ramp down.
This output is going straight to another IC as an input and shouldn't be feeding anything back towards the Zynq.