08-02-2017 03:44 AM
I am using ZYNQ series XC7Z020-2CLG484I SoC for my new design.
How to control the default status of selected I/Os to low.
I know I could able to make it high or 3-stated by PUDC_B pin.
08-02-2017 03:52 AM
@manumohanmm Below snippet from Page#49 of UG471 http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
08-04-2017 09:05 PM
Some more additional information:-
If you follow power-up sequence as per data sheet then IO state is in high-Z during power-up condition.
During configuration the default IO state depends upon PUDC_B pin input state. When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. So if you put external pull-down resister and your PUDC_B is High then you will get default low output during configuration.