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manumohanmm
Newbie
Newbie
3,446 Views
Registered: ‎09-02-2016

Zynq 7000 series IO's default status

Hi,

I am using ZYNQ series XC7Z020-2CLG484I SoC for my new design.

How to control the default status of selected I/Os to low. 

I know I could able to make it high or 3-stated by PUDC_B pin.

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2 Replies
gnarahar
Moderator
Moderator
3,442 Views
Registered: ‎07-23-2015

@manumohanmm Below snippet from Page#49 of UG471  http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

pullup down_attribute.JPG

- Giri
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umamahe
Xilinx Employee
Xilinx Employee
3,375 Views
Registered: ‎08-01-2012

Some more additional information:-

 

If you follow power-up sequence as per data sheet then IO state is in high-Z during power-up condition.

 

During configuration the default IO state depends upon PUDC_B pin input state. When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. So if you put external pull-down resister and your PUDC_B is High then you will get default low output during configuration. 

 

 

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