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Visitor
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Registered: ‎08-05-2020

Zynq-7020 I/O Clock Output Jitter

I'm using a Zynq-7020 (on an NI sbRIO-9627 board) to provide clock signals for sigma-delta ADCs. I'd like to know what the RMS jitter of the I/O clock output is, as I can't find a concrete number in the datasheet/TRM. This will help me decide whether I need a discrete clock generator or not. Thanks!

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Moderator
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Registered: ‎04-18-2011

Someone is likely to come along and give a much more detailed reply but you should understand that because the FPGA is programmable the output clock jitter is going to depend on 2 major factors

Input clock Jitter - this comes from the clock source you have on your board. 

System jitter on the clock distribution - in other words noise on VCCINT internal to the device. This is determined by two factors: the quality of your power supply design and the FPGA design itself. So a larger design with more switching is going to cause more jitter due to the current load on the VCCINT rail any variation on VCCINT will translate to clock jitter on the output of the BUFG. 

I would expect the quality of the clock needed for the sigma delta ADC should be very good. You need to consider what the ADC vendor says about clocking their device. 

Regards, 

Keith 

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Registered: ‎01-22-2015

@w00t 

Clocks generated by Zynq-7 (and many Xilinx FPGAs) typically come from the Clock Managment Tiles called the PLL or MMCM.   These clocks typically have too much jitter for use as the main clock input to an ADC.

Usually, we use the Xilinx IP called the Clocking Wizard to setup an MMCM or PLL.  As shown in the screenshot below, the final tab of the Clocking Wizard reports Peak-to-Peak jitter in picoseconds for the output clocks. 
CLK_WIZ_jitter.jpg

 

Peak-to-Peak jitter can be converted into other measures of jitter as described in Maxim document, AN462.   In AN462, you will find that a Bit-Error-Rate (BER) value is needed to convert from Peak-to-Peak jitter to RMS jitter.  Neither the Clocking Wizard nor Xilinx documentation gives us the value of BER.  However, it is generally though that Peak-to-Peak jitter is approximately 14x the RMS jitter, which equates to a BER of about 10^(-12).

You may find the discussion in the following post to be helpful.
https://forums.xilinx.com/t5/Other-FPGA-Architecture/FPGA-creates-main-clock-for-ADC/m-p/864059#M27388

Cheers,
Mark

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