08-04-2018 11:59 PM - edited 08-05-2018 12:00 AM
now I have some confusion. my z7100 board has 20 group lvds signals which connectted with 20 different boards( one group have lvds_clk/[0:0]lvds_tx /[0:0] lvds_rx)
XAPP585 show me that one group lvds should be used one pll/mmcm, shown like this
so my question is ： should 20 group LVDS can share PLL/MMCM?
many thanks for your any suggestion
08-05-2018 07:23 AM
So, first... This diagram comes from a specific app note which is about using the ISERDES to recover DVI or HDMI signals, which have the odd characteristic of the LVDS clock being 1/7th the frequency of the data... If your clock and data are the same frequency (which is more common), then this app note probably isn't for you...
So the next question is more about what you need to do for these signals. How fast is the clock? What is the timing relationship between the clock and the data - you have a single clock but both an input and output data - is the clock coming from the FPGA or coming from the external device? In either case, one direction is going to be similar to a source synchronous interface, and the other direction is going to be "worse than a system synchronous interface" - so timing in one direction is going to be significantly harder to deal with than the other.
Based on all this, you can start to make a decision as to whether you need some kind of dynamic capture or whether you can do it statically. If you can do it statically, you may not need an MMCM for the interface (the MMCM here is used specifically due to the 1:7 ratio of clock to data). In all cases, you will need to ensure that all 20 clocks come in on clock capable I/Os and in the same bank as their associated data.
But, ultimately, if you need an MMCM, and the clocks each come from a different board and each board has its own local oscillator, then, yes, you will need 20 MMCMs (which you likely won't be able to find on your device).
08-06-2018 06:40 PM
thanks for your information
all board has the same synchronize clock ---48KHz. so is this application can be used as statically?
I will evaluate all information you provide for me
many thanks ！
08-08-2018 10:25 AM
You didn't answer the question of "how fast is the clock" - or specifically, how fast is the data on these LVDS signals.
If the data is at 48KHz (or even a reasonable multiple of this), then these signals are so slow that a whole bunch of solutions become possible.
Tell us completely about what you want to do.
How fast are the data signals? How are the 20 LVDS clock signals related to one another? How do they relate to the 48kHz reference? How is the LVDS clock related to the RX (show a timing diagram)? How is the LVDS clock related to the TX (show a timing diagram)? How is the data on the LVDS signals formatted; it is clearly serial, since it is one bit - how is it framed?
If you give us information, we can give you meaningful answers.
08-12-2018 07:15 PM
Dear avrumv, thanks for your replay
The data is at 48KHz, but has 64 channels which is 32bit per channel ,so its bandwidth is 98.304M . I will use LVDS 1:1 at 125MHz.
All boards clock are synchronization, so LVDS TX I will use the local clock to parallel all 20 group LVDS.
My project top block diagram will work as the following
thanks for any suggestion！