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danwwright
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Registered: ‎10-12-2014

cannot compose a working .xds constraint file to implement xapp585 on an XC7A200T-3FFG1156 under Vivado

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I had a woking LVDS application on Spartan-6 devices by following xapp1064 (using ISE of course).  However now we are moving thje design to Artix-7 using Vivado.  It looks like xapp585 provides us exactly what we need- however Vivado fails for all of my attempts at composing a constraint file got the transceiver pins.  More specifically the constaints for locating the GTP tranciever pins on the XC7A200T-3FFG1156 is given below:

# 3 lanes IN:

set_property PACKAGE_PIN AK17 [get_ports clkin_n];
set_property PACKAGE_PIN AJ17 [get_ports clkin_p];
set_property PACKAGE_PIN AM16 [get_ports {datain_n[0]}];
set_property PACKAGE_PIN AL16 [get_ports {datain_p[0]}];
set_property PACKAGE_PIN AK15 [get_ports {datain_n[1]}];
set_property PACKAGE_PIN AJ15 [get_ports {datain_p[1]}];
set_property PACKAGE_PIN AK13 [get_ports {datain_n[2]}];
set_property PACKAGE_PIN AJ13 [get_ports {datain_p[2]}];

set_property DIFF_TERM TRUE [get_ports clkin_p];
set_property DIFF_TERM TRUE [get_ports clkin_n];
set_property DIFF_TERM TRUE [get_ports {datain_p[0]}];
...


set_property IOSTANDARD LVDS_25 [get_ports clkin_p];
set_property IOSTANDARD LVDS_25 [get_ports clkin_n];
set_property IOSTANDARD LVDS_25 [get_ports {datain_p[0]}];
...

# 3 lanes OUT:

set_property PACKAGE_PIN A23 [get_ports clkout_n];
set_property PACKAGE_PIN B23 [get_ports clkout_p];
set_property PACKAGE_PIN C22 [get_ports {dataout_n[0]}];
set_property PACKAGE_PIN D22 [get_ports {dataout_p[0]}];
set_property PACKAGE_PIN A21 [get_ports {dataout_n[1]}];
set_property PACKAGE_PIN B21 [get_ports {dataout_p[1]}];
set_property PACKAGE_PIN A19 [get_ports {dataout_n[2]}];
set_property PACKAGE_PIN B19 [get_ports {dataout_p[2]}];

set_property IOSTANDARD LVDS_25 [get_ports clkout_p];
set_property IOSTANDARD LVDS_25 [get_ports clkout_n];
set_property IOSTANDARD LVDS_25 [get_ports {dataout_p[0]}];
...

On my XC7A200T-3FFG1156 these PACKAGE_PIN's correspond to these signals:

# IN:

MGTPRXP0_113
MGTPRXN0_113
MGTPRXP1_113
MGTPRXN1_113
MGTPRXP2_113
MGTPRXN2_113
MGTPRXP3_113
MGTPRXN3_113
# OUT:
MGTPTXP0_216
MGTPTXN0_216
MGTPTXP1_216
MGTPTXN1_216
MGTPTXP2_216
MGTPTXN2_216
MGTPTXP3_216
MGTPTXN3_216

However synthesis files with an error:

There are only 10 usable IO banks in the device...

All of the general IO pins had already been specified for non-transceiver IO.  So what appears to be happening is that my specifications of my chosen locations for the transceiver pins are being IGNORED and Vivado is attempting to move these to the 10 banks of general IO (which fails of course as there's no more room in those banks).

I did look at the buildable "OrgVhdlVersion" and it's constraint file: top5x2_7to1_ddr_rx.xdc from xapp585.  The default build of this source looks like it's assuming a device of XC7K70T-1FFG676.  Looking into the locations for the transceiver pins on this part in top5x2_7to1_ddr_rx.xdc I find that the specified PACKAGE_PIN's DO NOT EXIST on the XC7K70T-1FFG676.  So there are no hints there.

I did look into pg168-gtwizard.pdf... but that speaks only of composing UCF files.  Can UCF files even be used under Vivado?  That doc briefly describes what must be in the UCF files- but gives NO SAMPLE of a correctly composed UCF file for configuring the transceiver pins.

Is there some essential documentation somewhere that will clarify how to impement xapp585 under Vivado?

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danwwright
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Registered: ‎10-12-2014
Again- never mind. This question is clearly answered under "Managing Unused GTP Transceivers" on page 219 of UG482 "7 Series FPGAs
GTP Transceivers".

Sorry for the waste of time...

View solution in original post

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danwwright
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Registered: ‎10-12-2014

Ah- never mind.  I've realized that xapp585 is not even using the transceivers.  So the LVDS pins in this design must go to the general IO banks.

But if I create a design in which the transceivers are unused- what to do with all of the transceiver-specific pins on our custom PCB?  Can these all be left inconnected?  Should some be grounded, etc.?

Our chosen part is the XC7A200T-3FFG1156 and the transceiver-dedicated pins appear in enormous number (see below).  How should these be tied on our PCB if we intend to never use the transceivers?

MGTAVCC_G10AG15
MGTAVCC_G10AG17
MGTAVCC_G10AG19
MGTAVCC_G10AG21
MGTAVCC_G10AJ14
MGTAVCC_G10AJ16
MGTAVCC_G10AJ18
MGTAVCC_G10AJ20
MGTAVCC_G11F14
MGTAVCC_G11F16
MGTAVCC_G11F18
MGTAVCC_G11F20
MGTAVCC_G11H15
MGTAVCC_G11H17
MGTAVCC_G11H19
MGTAVCC_G11H21
MGTAVTT_G10AJ22
MGTAVTT_G10AL13
MGTAVTT_G10AL15
MGTAVTT_G10AL17
MGTAVTT_G10AL19
MGTAVTT_G10AL21
MGTAVTT_G10AN14
MGTAVTT_G10AN16
MGTAVTT_G10AN18
MGTAVTT_G10AN20
MGTAVTT_G10AN22
MGTAVTT_G11B14
MGTAVTT_G11B16
MGTAVTT_G11B18
MGTAVTT_G11B20
MGTAVTT_G11B22
MGTAVTT_G11D13
MGTAVTT_G11D15
MGTAVTT_G11D17
MGTAVTT_G11D19
MGTAVTT_G11D21
MGTAVTT_G11F22
MGTPRXN0_113AK17
MGTPRXN0_116E13
MGTPRXN0_213AM18
MGTPRXN0_216E21
MGTPRXN1_113AM16
MGTPRXN1_116E15
MGTPRXN1_213AK19
MGTPRXN1_216C20
MGTPRXN2_113AK15
MGTPRXN2_116C16
MGTPRXN2_213AM20
MGTPRXN2_216E19
MGTPRXN3_113AK13
MGTPRXN3_116E17
MGTPRXN3_213AK21
MGTPRXN3_216C18
MGTPRXP0_113AJ17
MGTPRXP0_116F13
MGTPRXP0_213AL18
MGTPRXP0_216F21
MGTPRXP1_113AL16
MGTPRXP1_116F15
MGTPRXP1_213AJ19
MGTPRXP1_216D20
MGTPRXP2_113AJ15
MGTPRXP2_116D16
MGTPRXP2_213AL20
MGTPRXP2_216F19
MGTPRXP3_113AJ13
MGTPRXP3_116F17
MGTPRXP3_213AJ21
MGTPRXP3_216D18
MGTPTXN0_113AP17
MGTPTXN0_116A13
MGTPTXN0_213AP19
MGTPTXN0_216A23
MGTPTXN1_113AP15
MGTPTXN1_116C14
MGTPTXN1_213AP21
MGTPTXN1_216C22
MGTPTXN2_113AM14
MGTPTXN2_116A15
MGTPTXN2_213AM22
MGTPTXN2_216A21
MGTPTXN3_113AP13
MGTPTXN3_116A17
MGTPTXN3_213AP23
MGTPTXN3_216A19
MGTPTXP0_113AN17
MGTPTXP0_116B13
MGTPTXP0_213AN19
MGTPTXP0_216B23
MGTPTXP1_113AN15
MGTPTXP1_116D14
MGTPTXP1_213AN21
MGTPTXP1_216D22
MGTPTXP2_113AL14
MGTPTXP2_116B15
MGTPTXP2_213AL22
MGTPTXP2_216B21
MGTPTXP3_113AN13
MGTPTXP3_116B17
MGTPTXP3_213AN23
MGTPTXP3_216B19
MGTREFCLK0N_113AH14
MGTREFCLK0N_116G16
MGTREFCLK0N_213AH20
MGTREFCLK0N_216G18
MGTREFCLK0P_113AG14
MGTREFCLK0P_116H16
MGTREFCLK0P_213AG20
MGTREFCLK0P_216H18
MGTREFCLK1N_113AH16
MGTREFCLK1N_116G14
MGTREFCLK1N_213AH18
MGTREFCLK1N_216G20
MGTREFCLK1P_113AG16
MGTREFCLK1P_116H14
MGTREFCLK1P_213AG18
MGTREFCLK1P_216H20
MGTRREF_213AH22
MGTRREF_216G22
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danwwright
Contributor
Contributor
500 Views
Registered: ‎10-12-2014
Again- never mind. This question is clearly answered under "Managing Unused GTP Transceivers" on page 219 of UG482 "7 Series FPGAs
GTP Transceivers".

Sorry for the waste of time...

View solution in original post

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