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donkeyhot
Visitor
Visitor
7,500 Views
Registered: ‎10-29-2013

cclk termination in 7 series

Hi! I'm designing a board with kintex 7. I decided to use BPI NOR flash for configuration in synchronous mode. As shown in KC705 Ev. board schematic there is a reserved place for AC termination (parallel connection of a resistor in series with a capacitor) of CCLK line. AR 41782 says that ringing was fixed in 7 series. I'm a bit confused about the reason of reserving place for R and C on the CCLK line.

As for me, AC termination of CCLK line is needed when the length of the line is rather long. If the trace is relatively short (  for example < 5 inches) there is no need of termination. Correct me, if i'm wrong.

 

And one more question, is it ok to use BPI NOR flash in asynchronous mode for updating multiboot image  ("update bitstream") after configuration? I mean remote programming (when we send bitstream via ethernet and fpga programm its own flash)

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aher
Xilinx Employee
Xilinx Employee
7,484 Views
Registered: ‎07-21-2014

Hi,
Regarding your second question,
Yes, you can use PBI NOR flash in asynchronous mode. please refer XAPP1081
http://www.xilinx.com/support/documentation/application_notes/xapp1081-quickboot-remote-update.pdf

-Shreyas
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umamahe
Xilinx Employee
Xilinx Employee
7,449 Views
Registered: ‎08-01-2012

  1. Q) --As for me, AC termination of CCLK line is needed when the length of the line is rather long. If the trace is relatively short (  for example < 5 inches) there is no need of termination. Correct me, if i'm wrong.

 

  • The Xilinx recommendation made based on wide characterization testing and safe to follow. It is more generic recommendation by considering wider corner cases. 
  • For other scenarios (for example < 5 inches in your case) it may work but there is no guarantee because it was not tested by Xilinx. I recommend to do run IBIS simulations and verify if you are planning with non-recommended scenario

 

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