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fogl
Explorer
Explorer
1,413 Views
Registered: ‎02-04-2013

changing clock input pin position

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I am having problem with modification of my design. I changed the clock input pin position from first MRCC input (located at the corner of the die) to the second MRCC input (located in the middle of the die). The "new" design fails timing at several paths (Intra-Clock - setup).

 

Is this typical that the design is so sensitive regarding the clock placement - I was expecting better results with the clock pin located at the middle of the die?

 

Regards

Klemen

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hpoetzl
Voyager
Voyager
1,972 Views
Registered: ‎06-24-2013

Hey Klemen,

 

Thank you for your reply,

You're welcome!

 

How can i reset the design?

In the 'Design Runs' tab, there is a 'Reset Runs' button and context menu option.

 

So if i am close to the design margins, i can probably expect some problems later, if i change something.

Correct.

 

I am running the design at 100 MHz - i assume this is not critical frequency.

No for 7Series the critical limit starts at 240MHz and goes up to 500MHz depending on what you are doing.

Of course, you can still hit critical timing problems way below that or just have too strict constraints.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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hpoetzl
Voyager
Voyager
1,403 Views
Registered: ‎06-24-2013

Hey Klemen,

 

Is this typical that the design is so sensitive regarding the clock placement?

Really depends on the design.

If you are operating at the limits of the FPGA, the slightest change can tip you over the edge.

That said, did you place and route from scratch or did you reuse the existing placement?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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fogl
Explorer
Explorer
1,390 Views
Registered: ‎02-04-2013

Thank you for your reply,

 

I run Synthesis and Implementation after the constraint change. I thought Vivado starts all over again, not from some previous design step. How can i reset the design?

 

So if i am close to the design margins, i can probably expect some problems later, if i change something. I am running the design at 100 MHz - i assume this is not critical frequency.

 

Regards

Klemen

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hpoetzl
Voyager
Voyager
1,973 Views
Registered: ‎06-24-2013

Hey Klemen,

 

Thank you for your reply,

You're welcome!

 

How can i reset the design?

In the 'Design Runs' tab, there is a 'Reset Runs' button and context menu option.

 

So if i am close to the design margins, i can probably expect some problems later, if i change something.

Correct.

 

I am running the design at 100 MHz - i assume this is not critical frequency.

No for 7Series the critical limit starts at 240MHz and goes up to 500MHz depending on what you are doing.

Of course, you can still hit critical timing problems way below that or just have too strict constraints.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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fogl
Explorer
Explorer
1,285 Views
Registered: ‎02-04-2013

Thank you for your comment. I did try to Reset Runs and the result was the same.

So it seems i will have to modify the design.

 

Regards

Klemen

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