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Registered: ‎05-28-2018

clk wizard always miss locked

hardware zynq_7020

software --vivado2018.2

ip  clock wizard6.0 

input  25mhz,rstn

output 10mhz,locked

cconfig :mmcm  freq syn,phase aligh,safe starup, mini power ,balanced

question: when i monitor lock signal ,i found that locked signal is periodic signal, its periodic is about 92us,and lower level is about 18.44us,and rstn signal is normal, what's wrong?

ps when i simulate,it does not happen,but when i download bit doc to soc ,it appear.

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Registered: ‎04-18-2011

Re: clk wizard always miss locked

The first place to look is the input clock.
The datasheet will tell you that the maximum allowed input jitter is 20% of the i out clock period or 1ns max.
What does the clock you provide look like. Try a simple build with no mmcm and route the incoming clock to a pin and scope it.
Another test for the input clock quality is change the output frequency to if it will lock with different settings.
If the clock is good then the next place to look is the power supplies. Is vccint noise causing too much jitter on the clock path or indeed the feedback path?
Next look at vccaux is that noisy is it outside the recommended tolerance on the rail?

Next simplify the mmcm.
Get rid of the safe start up option and the minimize power option see if it works then.

Have you tried a reset? Reset the mmcm and see if it locks.

Can you share the M, D, and O values set by the wizard?
Don’t forget to reply, kudo, and accept as solution.
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