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914 Views
Registered: ‎01-07-2018

clock mux 8:1

Hi, 

 

In my design, I have a variety of clocks generated out of MMCM. 

With a 3 bit select signal, I need to multiplex these clocks and generate 

a single clock output. 

 

I tried cascaled BUFGMUX and as expected, it failed in Vivado routing stage. 

 

Please suggest which is the best way to solve this . 

 

Thanks,

Babu

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3 Replies
pedro_uno
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Registered: ‎02-12-2013

I'm guessing you don't care about propagation delay through any of these mux paths. If that is true you can probably just mux the clocks as if they were normal (non-clock) signals then put a bufg on the output of the mux.
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DSP in hardware and software
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avrumw
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Registered: ‎01-23-2009

There is no way to do this "well". Clock MUXing done right (with a BUFGMUX) in an FPGA is normally only two clocks. Some cascading is possible, but there are limits. Furthermore, cascaded BUFGMUX have long and uncompensated delays, meaning the phase of the resulting clock is effectively unknown...

 

In general, the solution is to find a way to do this without MUXing the clock. Many times people try to do this for reasons that have better solutions that don't involve MUXing lots of clocks...

 

So tell us what you are trying to accomplish. What is the original problem that you think you can solve with MUXing multiple clocks? If possible, we will give you an alternative approach to solving the problem that does not involve clock MUXing...

 

Avrum

851 Views
Registered: ‎01-07-2018

Hi avrumw, 

 

Thanks for the immediate response. 

 

Our ASIC design works on a variety of source clocks to JESD 204B transmitter design and the destination clock 

of the JESD204B transmitter is fixed. The design has FIFOs take care of the various input rates. 

 

The source clock frequency depends on the effective sampling rate to the transmitter. 

For us to validate this in FPGA, we need to create a variety of such scenarios, each scenario

operating on a specific frequency. There are 8 such clock scenarios. 

The design gets a single clock source input that is the mux output of these 8 clocks. 

 

The requirement is, from reset to reset, the input clock frequency remains the same, so there is no 

dynamic frequency change on the fly. 

 

The frequencies to be muxed (in MHz) are 15.6125, 20.833, 31.25, 41.667, 62.5, 83.333, 103.25, 125.

The reference clock frequency to the MMCM = 156.25 MHz

 

Alternatively, it is also okay to have a programmable MMCM that gets a control port which the user can change. 

How do we achieve this?

 

Thanks,

Babu

 

 

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