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Adventurer
Adventurer
2,581 Views
Registered: ‎03-15-2016

clock routing

Hi, I have a local 24Mhz clk feed into the FPGA MRCC PIN, then instance a MMCM to do clk synthesis 2 clock output. i set the output drive in mmcm with no buffer(becasue i don't want bufg cascading), and connect the clkfb_out direct with clkfb_in, connect the two outputs to a BUFGMUX. I wonder what kind of clock routing resource did the MMCM output clock use. so i checked the implemented design, found that, the delay is 190ps..i don't understand the routing node? i think it is still use Horizontal routing resource. but why it delay so much.
clock delay.png
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Adventurer
Adventurer
2,580 Views
Registered: ‎03-15-2016

Re: clock routing

add routing node info
routing nodes.png
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