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alauddinm
Newbie
Newbie
604 Views
Registered: ‎09-17-2018

clocking issue during probing debug signals

Hi All,

i have a design which has 125Mhz Ip clk coming from onboard oscillator.

I then generated many frequencies(div2,div4 etc) using MMCM_ADV for different modules.
Now i wanna probe the signals in each module and see them in logic analyzer.

But tool is throwing error like the clock for debug_hub is not a free running.

so is it like each and every ILA needs clock coming from onboard osc ?
But its frequency is diff then the frequency of signals i probed as they wer running on MMCM generated clocks.

How can i probe those signals? what are some standard industrially accepted strategies ?

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pthakare
Moderator
Moderator
597 Views
Registered: ‎08-08-2017

Hi @alauddinm

Which clock is connected to Debug Core ?  Can you share the Schematic ?

Please check this  Answer record for similar issue.

https://www.xilinx.com/support/answers/64764.html

 

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jheslip
Xilinx Employee
Xilinx Employee
551 Views
Registered: ‎06-30-2010

i guess you are using an MMCM for the different clock speeds, is the RST of this controlled by an VIO?

Where are you getting the error, in the Vivadoflow or when you connect via JTAG?

 

You can have multiple clocks driving different ILAs, i suggest though having one that runs off the free running clock that monitors the MMCM and ensures that it is locked as until it is the other ILAs should not be used.

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