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479 Views
Registered: ‎03-03-2017

clocking pin to bufg on opposite side of FPGA

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Quick question.  I am using a 7 series device (Artix 7 xc7a75tfgg676) and Vivado 2019.1.   On our hardware I did not have the clocking pins assigned optimally it seems and I have a clock pin on the NORTH side of the FPGA (Bank16) and need to get that pin into a BUFGMUX on the south side of the chip.   Is there any way I can do this?   The pin being used in Bank 16 is an SRCC pin.

Thanks for any help.

Tim

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Guide avrumw
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444 Views
Registered: ‎01-23-2009

Re: clocking pin to bufg on opposite side of FPGA

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I presume your problem is that one of the clock inputs to the BUFGMUX comes in on a pin in the top half of the device, and the other input to the BUFGMUX is somehow associated with the bottom half of the device (either from an SRCC in the lower half, or from an MMCM in the lower half).

If neither of these can be moved, then you have a problem - you cannot route this using dedicated routing. I believe that you can use CLOCK_DEDICATED_ROUTE=FALSE for one of the two clocks, but that will bring the clock through the fabric routing. This means:

  • you will have an essentially unknown insertion delay on that clock (that can vary from run to run)
    • this means that the clock is essentially useless for clocking input or output interfaces
  • the clock will pick up a fair amount of jitter as it passes through the fabric logic
    • I am pretty sure the tool understands this and will factor it in to timing calculations that use this clock

This is a pretty non-ideal solution, but if you have no other...

Avrum

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453 Views
Registered: ‎01-22-2015

Re: clocking pin to bufg on opposite side of FPGA

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Hi Tim,

The 32 global clock buffers, BUFGCTRL, found in the Artix-7 are located in the center of the die/device and divided into two groups of 16ea called the top-half and bottom-half groups  - see page 36 of UG472(v1.14).
BUFGCTRL_ARTIX7.jpg

The BUFGMUX and other clock buffers (eg. BUFG) are constructed by the Vivado tools from a BUFGCTRL.

Table 1-1 in UG472 says that an SRCC pin can directly drive any of the 16ea BUFG/BUFGCTRL/BUFGMUX found in the same half  (top/bottom) of the device where the SRCC pin is located.  

Normally, in your design, you can simply route the SRCC pin to a BUFGMUX and the tools will find a BUFGMUX in the correct half of the device for you. 

Finally, to your question:

... need to get that (SRCC) pin into a BUFGMUX on the south side of the chip.
Are you sure the BUFGMUX needs not to be on the south (bottom-half) of the device?  The output of a BUFGMUX that is located on the north (top-half) of the device can reach any "clocking point in the fabric and I/O".

I am questioning your question because I actually can't find a way to reach a BUFGCTRL/BUFGMUX on the bottom-half from a SRCC pin on the top-half.

Mark

 

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Guide avrumw
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445 Views
Registered: ‎01-23-2009

Re: clocking pin to bufg on opposite side of FPGA

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I presume your problem is that one of the clock inputs to the BUFGMUX comes in on a pin in the top half of the device, and the other input to the BUFGMUX is somehow associated with the bottom half of the device (either from an SRCC in the lower half, or from an MMCM in the lower half).

If neither of these can be moved, then you have a problem - you cannot route this using dedicated routing. I believe that you can use CLOCK_DEDICATED_ROUTE=FALSE for one of the two clocks, but that will bring the clock through the fabric routing. This means:

  • you will have an essentially unknown insertion delay on that clock (that can vary from run to run)
    • this means that the clock is essentially useless for clocking input or output interfaces
  • the clock will pick up a fair amount of jitter as it passes through the fabric logic
    • I am pretty sure the tool understands this and will factor it in to timing calculations that use this clock

This is a pretty non-ideal solution, but if you have no other...

Avrum

View solution in original post

435 Views
Registered: ‎03-03-2017

Re: clocking pin to bufg on opposite side of FPGA

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@avrumw ,

   You are correct. 
   The strange thing is that if I implement the design with one block not instantiated (which has nothing to do with any clock bufs) the design successfully implements.    I will have more detail on why this happens tomorrow and will try and update this post with that info.  
   Otherwise regarding my question in this post you have answered it.  
Thanks.  
Tim

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Registered: ‎03-03-2017

Re: clocking pin to bufg on opposite side of FPGA

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@avrumw or markg@prosensing.com 

   Do you know if an MRCC pin can drive a BUFG on the oppisite side of the FPGA?

Thanks.

Tim

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Guide avrumw
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385 Views
Registered: ‎01-23-2009

Re: clocking pin to bufg on opposite side of FPGA

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Do you know if an MRCC pin can drive a BUFG on the oppisite side of the FPGA?

No, it cannot.

The only "additional" capability of an MRCC over an SRCC is that it can also drive the BUFMR which allows connections to the BUFR and BUFIO in the neighbouring regions. It has no impact on the global clock connectivity.

Avrum

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Registered: ‎03-03-2017

Re: clocking pin to bufg on opposite side of FPGA

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@avrumw ,

   Thanks for the confirmation.

   Another question.   Is there some other BUF type that I can drive which can then drive a BUFG on the opposite side of the chip?   For instance can the NORTH pin drive a BUFH which would then drive into a BUFG in the SOUTH side?   I am looking for options to make this hardware layout function.

Thanks.

Tim

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Guide avrumw
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365 Views
Registered: ‎01-23-2009

Re: clocking pin to bufg on opposite side of FPGA

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No matter what, you are going to have "unconventional" routing. The question is what do you need to do with this "north side" clock - is it merely a frequency reference, or is it also used for clocking an interface.

If it is used for clocking an interface, then there is nothing you can do - all solutions will introduce large uncompensated (and potentially route-to-route variable) insertion delay that will mess up any interface timing. If it is only used as a clock reference then the insertion delay isn't important, and what you want to minimize is jitter.

The only solution that I can suggest that will minimize jitter is taking the clock from the north, running it through a BUFG on the north side and then to the BUFGMUX on the south side (simply inserting the extra BUFG in your RTL will probably be sufficient, the tools can figure out where to place it). This will have very long clock insertion (an extra BUFG and global clock tree), but will, at least, stay on isolated routing for the entire path. It, of course, uses an extra BUFG. This will still require CLOCK_DEDICATED_ROUTE=FALSE (since this isn't really a "dedicated" path), but it's probably the best you can do.

Avrum

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Registered: ‎03-03-2017

Re: clocking pin to bufg on opposite side of FPGA

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@avrumw ,

   This makes perfect sense.  Luckily it is used as a reference.   Thanks for all your inputs.    I have learned a lot with this issue.  
Tim

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Registered: ‎01-22-2015

Re: clocking pin to bufg on opposite side of FPGA

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@tim_severance 

Why do you need a BUFG in the south side of the FPGA? 

A BUFG in the north side of the FPGA can reach every clocking point in the fabric and IO of both the north side and the south side.  That is, a BUFG in the north side can send a clock to a register located in the south side.

Mark

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Registered: ‎03-03-2017

Re: clocking pin to bufg on opposite side of FPGA

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markg@prosensing.com ,

   I am using a BUFG_MUX setup to select either a clock from the NORTH side of the chip or a clock from the SOUTH side of the chip.

   I am able to get around my issues by using set_property CLOCK_DEDICATED_ROUTE FALSE constraint.

   Through this forum interaction I think I have learned to not fear using this constraint since I now have a better idea of what it is doing.

Tim

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