10-22-2019 08:34 AM
How to compile a VHDL project for XC4003E device?
I tried ISE 4.1, but it does not support XC4003E device.
I tried ISE 4.2, but if does not manage VHDL file.
10-22-2019 05:56 PM
This is very old stuff – but here’s some places to help you search for the tools you need.
AR#33560 talks about tools for working with the XC4000 devices. It says that ISE v4.2 supports the devices but has “ …no design-entry or synthesis support for these devices..” and that “...you must obtain a third-party synthesis or schematic toolset to produce an EDIF file.”
So, it seems that your job is to find a synthesis tools that converts your VHDL into an EDIF file, which can then be imported into ISE v4.2.
An old document <here>, talks about using a “VHDL toolbox from Cadence” to synthesize VHDL designs and produce the needed EDIF file, which can then be used by ISE to place and route the design.
Another old document <here> talks about using “EXEMPLAR's Leonardo” to create the needed EDIF file.
10-22-2019 11:42 PM
Back in the '90s (when the XC4000E family was still current), I used Synplify by Synplicity for compiling VHDL.
Synplify still exists as a product. It is owned by Synopsys now. I suspect you will have problems finding an old version that still supports these devices though.
10-23-2019 02:42 AM
You may be able to use the newer Xilinx tools to produce the EDIF file needed for ISE v4.2.
For example, see the Vivado tools write_edif command described on page 27 of UG901(v2019.1).
Newer versions of ISE can also create the EDIF file (search for information on ngc2edif.exe).
10-29-2019 10:45 AM
I have created the EDIF file with VIVADO 2019.1 (I used command write_edif).
But, once imported the EDIF file in ISE4.2 and started "Implement Desing", I had many errors of this type:
ERROR:NgdBuild:604 - logical block '<name of the block>' with type 'LUT5' is unexpanded. Symbol 'LUT5' is not supported in target 'cx4000e'.
10-29-2019 05:21 PM
The Electronic Data Interchange Format (EDIF) file is supposed to be an industry standard file format for specifying a design netlist. Although, I read <here> that since the release of EDIF 4 0 0 (in 1996), the EDIF standards organisation has essentially dissolved.
So, I think it is going to be hard for you to get your VHDL into that old XC4003E.
It appears that Vivado has synthesized some of your VHDL to be LUT5 components. Look-Up-Tables (LUTs) have been a common component in FPGAs for years. They were small at first (LUT1, LUT2, LUT3, LUT4) but have (since the XC4003E) gotten larger (LUT5, LUT6). The error you are seeing indicates (I think) that the LUT5 used by Vivado synthesis was not yet available in the XC4003E.
Perhaps you can try ISE versions after v4.2 that were able to do synthesis and to create EDIF files. Maybe the EDIF files created this way will contain only components that are recognized by ISE v4.2. <Here> you will find release notes for many of the ISE versions. Perhaps these release notes will help you find what is needed. Also, in these release notes are lists of third-party vendors who have synthesis tools that are compatible with ISE.
Good luck! -sorry I couldn’t be of more help.