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Adventurer
Adventurer
5,968 Views
Registered: ‎06-16-2016

customisation of MIG 7

HI  I'm Lalith  , I need to interface QDR2+ to Virtex 7 , but while creating MIG core ,im not finding my memory part in MIG core option .

 

so I selected nearest part and in custom part option , but in custom part there is no option to change/set a setup and hold time of core .

 

Please tell me complete steps for ,how to create custom part for QDR2+ with different timing parameters ,   

 

Thank you 

Lalith

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Xilinx Employee
Xilinx Employee
5,963 Views
Registered: ‎07-11-2011

Re: customisation of MIG 7

@lalithkumar

 

You have to choose the base part that matches all the timing parameters with your actual part. Underlying timing parameters are based on read latency I beleive 2 or 2.5

QDRII+ SRAM custom part wizard allows only address width option to have differnet densities and nothing more.

 

Hope this helps

 

-Vanitha 

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Adventurer
Adventurer
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Registered: ‎06-16-2016

Re: customisation of MIG 7

 

Thank you for replying,

@vsrunga

 

Yes i have selected part in custom part option but only setup and hold time are miss matches by 0.1 ns(core is fastter than my physical part)

 

thats why i asked is there any chance (RTL) of changing Setup and hold time of core. if it there please tell me to do it.

 

or This 0.1 ns is make any conflicts when physical qdr2+ interfaced. 

 

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Adventurer
Adventurer
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Registered: ‎06-16-2016

Re: customisation of MIG 7

@vsrunga

 

sorry its not 0.1 ns its 10 ns.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: customisation of MIG 7

@lalithkumar

 

Check if rea dlatency value of your part matches with the base part. If yes you can go ahead 

You can run the core at lower frequencies and test in HW to see if it really has any issues. Provided timing is met and enough margin exists 0.1 ns should not be a problem

 

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Adventurer
Adventurer
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Registered: ‎06-16-2016

Re: customisation of MIG 7

 @vsrunga

Yes my physical part is also has 2.5 read latancy , (i should operate memory at 500>= Mhz)

but Setup and hold time are differ by 10 ns than core part, wat to do now .

please help me will it create timing issue. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: customisation of MIG 7

@lalithkumar

 

Can you share your QDRII+SRAM actual part and base part details and their datasheet links?

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