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Registered: ‎10-01-2013

design migration from Vivado 2016.1 to Vivado 2016.2

Hello support;


I have a design that works perfectly on Vivado 2016.1. It uses scatter gather DMA with PCIe Gen3x4 and MIG DDR3 and some memory blocks.

When I migrate on Vivado 2016.2, I see block memories has minor modifications and PCie has also minor modifications.

I see the MIG has major modification from version 3.0 to 4.0.

I use the IP upgare tools of Vivado and it seems working fine I did not get any error message.

I export to tcl and re run; i generate the bitstream.


BUT on board when i test performances with Vivado 2016.1 I have 2500Mbytes/sec and 110000bytes/sec with Vivado 2016.2.

Are you sure there is no modification in the PCIe credits management???

Can you please tell me why my performances drop off and how to solve this critical issue.


Thank you

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