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Visitor
Visitor
9,337 Views
Registered: ‎09-02-2015

differential I/O in a 3.3V domain

HI,

 

I need to implement both differential input and differential output in a 3.3V I/O domain. I cannot find an I/O type that will allow this.

 

How do I implement differential I/O at 3.3V?

 

These signals are on banks 14, 15 and 16 and are in conjunction with single ended 3.3V (LVCMOS33) I/O pins on these banks.

 

The device is an Artix 7, XC7A35T.

 

Thanks.

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Xilinx Employee
Xilinx Employee
9,331 Views
Registered: ‎02-16-2014

Hi,

 

You can download the package fiels for your device from the below link.

http://www.xilinx.com/support/packagefiles/artix-7-pkgs.htm

 

In the package file you can figure out which I/Os are differential I/Os.

 

Cross-check if those banks are HR or HP banks.

In HR banks 3.3V I/O standards are supported and in HP banks upto 1.8V I/O standrads are supported.

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Visitor
Visitor
9,321 Views
Registered: ‎09-02-2015

HI, Thanks for getting back to me.  Unfortunatly you have mis-read my question.

 

I am using the correct banks and I have set the VCC to the correct level.

But, I cannot find any way within Vivado to allow me to select a differential input or output at 3.3V.  All the available options are 1.8V, 1.5V or 2.5V.

 

I need a way to configure the differential pairs (_P and _N pair) to be used within a 3.3V bank.

 

 

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Xilinx Employee
Xilinx Employee
9,318 Views
Registered: ‎02-16-2014

HI,

 

There is no differential I/O standard that supportes 3.3V.That is the reason you are not seeing them in Vivado GUI.

You need to differential I/O standards  LVDS, Mini_LVDS, RSDS, PPDS, BLVDS, and differential HSTL and SSTL

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Visitor
Visitor
9,314 Views
Registered: ‎09-02-2015

Yes, exactly, But I need a 3.3V differential receiver and a 3.3V differential driver (this is what the attached hardware requires)

How can I implement a 3.3V differential input and output?

 

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Xilinx Employee
Xilinx Employee
9,310 Views
Registered: ‎02-16-2014

Hi,

 

Some of the older devices used to support LVDS_33 but 7-series devices don't support this I/O standard.

Please see this AR and check if it helps.

http://www.xilinx.com/support/answers/43989.html

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Visitor
Visitor
9,307 Views
Registered: ‎09-02-2015

So I can power my HR banks at 3.3V, use 3.3V single ended inputs and outputs, but I cannot configure the exact same hardware for differential use?

 

This seems to be a limitation of Vivado and not the hardware within the FPGA.

 

(BTW, I believe I can configure the inputs to be differential at 3.3V by selecting TDMS33 as the standard, but this is not suitable for output as this requires external 50R pull-ups) - I found this out by trial and error!

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Guide
Guide
9,301 Views
Registered: ‎01-23-2009

As other people have stated, there is no such I/O protocol - there is no differential signalling standard that uses 3.3V swings. So, first be certain that you external device really needs this - I have never encountered one that does...

 

But, if is the case that you must use 3.3V signalling, you can probably mock it up...

 

For the outputs, configure two adjacent pins (the P and N of the pair) both as LVCMOS33 (with a 3.3V VCCO), and simply drive the P and N to opposite values. Ideally these should be done from the IOB flip-flops. Now you just need to terminate them like differential signals; this will have to be done outside the FPGA (since the internal termination can't be used in this setup), and the value of the termination resistors will have to be determined by your external devices needs - again, there is no "standard" for this, since there is no 3.3V differential standard.

 

For the inputs, you will need to use LVDS_25 inputs. The good news is that if done carefully you can place this in the same bank as the outputs, since you don't need VCCO for an LVDS_25 input as long as

  - you don't use the DIFF_TERM (so you will need external termination)

  - you don't drive the voltages too high so as to forward bias the protection diode

  - you provide enough differential swing

 

These should all be able to be done by choosing appropriate termination resistors between the external device and your FPGA.

 

Avrum

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Teacher
Teacher
9,292 Views
Registered: ‎07-09-2009

Hi

 

can you share with us what it is your driving / receiving to / from please.

 

Quite often specs of boards are a bit less than engineering level,

  

I have seen LVDS and PECL been described as 3v3 , as the driver and receiver chips are powered off 3v3, even though the actual signaling levles are not 0 to 3v3.

 

Do you knwo what chip the far end uses to send and receive the signals,

 

 

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Visitor
Visitor
9,289 Views
Registered: ‎09-02-2015

I appreciate that there are few 3.3V differential standards' but there are a lot of devices that operate in a 3.3V domain that require adifferential clock.  For this project this is required as the clock to a high speed DAC.  It is a 3.3V device with single ended data bus and a differential clock.  Yes, I could use two outputs and put an ivnerter between them, and that will probably work OK.

I also have a 3.3V distributed differential clock that comes into the FPGA.

 

It must be possible for the FPGA to implement 3.3V differential drives and receivers as it can do this if you connect the VCC to 1.8 or 2.5V, but why does it not let you do this when you connect VCC to 3.3V?

 

I have tried what you suggest for the input (specifying them as LVDS_25) , but Vivado generates an error stating that I cannot combine 2.5V and 3.3V I/O in the same bank!

 

What I have found is that if I define the input as TMDS_33 then it will allow a 3.3V differential input to co-exist on the same bank as 3.3V single ended ins and outs.

 

It is obvous that the actual hardware of the FPGA can operate in differential modes at 3.3V, but it is Vivado that is limiting or removing this feature.

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Visitor
Visitor
8,364 Views
Registered: ‎09-02-2015

As I mentioned, the devices I am interfacing to are not 'boards' but other components on my board, in this case a DAC, and ADC and a clock distribution device.

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Guide
Guide
8,363 Views
Registered: ‎01-23-2009

I have tried what you suggest for the input (specifying them as LVDS_25) , but Vivado generates an error stating that I cannot combine 2.5V and 3.3V I/O in the same bank!

 

Are you sure you have set DIFF_TERM to FALSE? If so, then this is a bug in the tools. UG471 v1.5, table 1-55, footnote 1 clearly states that this is legal. If the tool disagrees, then file a webcase.

 

Avrum

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Visitor
Visitor
8,358 Views
Registered: ‎09-02-2015

Thanks, I will try that and let you know. (btw, where is DIFF_TERM defined?)

Although I do seem to have a solution for the inputs by defing them as TDMS_33.

 

BUT, I do not have a solution for the outputs

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Xilinx Employee
Xilinx Employee
8,357 Views
Registered: ‎01-03-2008

@ianharvey you wrote:

> I appreciate that there are few 3.3V differential standards' but there are a lot of devices that

> operate in a 3.3V domain that require a differential clock. 

 

You need to seperate the voltage supply and the input characteristics.  It is extremely likely that differential clock input to your DAC is standard LVDS with a 1.25V common mode and a +/-200mV swing while using a VCC of 3.3V.

 

Artix-7 HR banks required that LVDS oututs have a VCCO of 2.5V and using anything else will not work.

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
8,355 Views
Registered: ‎09-02-2015

As it is a 3.3V device I have connected to the same bank as the data bus for this device, all 3.3V interfaces.

I do not have any  2.5V devices or power rails on my design, only 1.8 and 3.3V.

 

I therefore cannot connect this clock to a 2.5V I/O bank, it must be connected to the 3.3V I/O bank.

 

I have found that the DAC does have a 'single ended' clock mode also, so I will modify my hardware to take the single ended clock.

 

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Visitor
Visitor
8,352 Views
Registered: ‎09-02-2015

HI, I have found that if the 'IN_TERM' is set to none then Vivado will allow this input to be declared as LVDS_25 when mapped to a 3.3V HR bank. 

I had inadvertantly enabled the terminator.

 

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Teacher
Teacher
8,348 Views
Registered: ‎07-09-2009

Ok, so not boards, 

   but can you tell us which devices please so we canlog this for future reference.

 

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Xilinx Employee
Xilinx Employee
8,324 Views
Registered: ‎01-03-2008

> I do not have any  2.5V devices or power rails on my design, only 1.8 and 3.3V.

 

If you want to have LVDS outputs from the Artix-7 device then you will need to add a 2.5V power regulator.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
8,308 Views
Registered: ‎09-02-2015

Thanks, I am aware of that, I would need a 2.5V power supply to have a 2.5V LVDS signal.  That wasnt my question!

 

So to confirm:  The Vivado software will not allow you configure a 3.3V differential output drive, even though the hardware of the FPGA would probably support it?

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Teacher
Teacher
8,304 Views
Registered: ‎07-09-2009

Hi

 

you sound well feed up,

 

can you tell us what the ADC and DAC chips are,

   most of these ADC / DAC chips have been used by others, so we can help you

 

 

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Xilinx Employee
Xilinx Employee
6,816 Views
Registered: ‎01-03-2008

> even though the hardware of the FPGA would probably support it?

 

No, the Artix-7 FPGA output circuits do not support LVDS at 3.3V. 

 

TMDS_33 that you mentioned earlier in this thread is a very different IOSTANDARD than LVDS.  It is differential, but it will not have the same performance or electrical specifications and requires external pullup resistors.

 
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
6,813 Views
Registered: ‎09-02-2015

Thanks for all your help, this has confirmed that I cannot use 3.3V differential outputs even if I wanted to.

(luckily I can use them single ended for this application)

 

Yes, I may sound fed up but that is because I cound not seem to get a straight answer here, yes I am perfectly aware that to use a different volatge standard as an output I need to set that bank at that output voltage, burt all along what I was asking was 'is there a way to confgure the outputs of the HR banks to operate as differential in a 3.3V domain'

 

By the way, what would happen if i 'told Vivado' that I was using all the pins on that HR port as 2.5V logic (then I could have single ended and differential mixed on the bank), but actually connected the VCCO to a 3.3V supply?  Would that get over the problem or would that cause some issues within the device?

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Xilinx Employee
Xilinx Employee
6,807 Views
Registered: ‎01-03-2008

> Would that get over the problem or would that cause some issues within the device?

It would not get over the problem.  The LVDS output circuits would detect that the voltage is too high and will disable to circuits to prevent damage to the device.

 
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Teacher
Teacher
6,800 Views
Registered: ‎07-09-2009

Hi

 

were all trying to help you

    but you do have to answer the questions we ask for us to help you.

 

For a 3v3 differential output, why not drive the pins of the FPGA with inverse signals,

    Ensure you have the output registers enabled in the IOB and use in DDR mode.

       quite a standard way, 

          

I'd still like to knwo what ADC and DAC your driving, 

    Ive used lots of ADI, TI, Maxim, et all, and can't rember seeing a real 3v3 differential part for ages,

       If they are high speed they use LVDS

.

 

I could be saying the obviouse here, 

   if so appologise.

 

But if your now using single ended not differential for the signaling and clock,

      it would be worth checking you have the correct termination at the correct place 

             and the noise , high quality ADC's have differential clocks and data to stop the noise

                  and ground bounce interfearing with the ADC.

 

  Just a thought 

 

Also if its one of the fast ADC or DAC's, then set up / hold timming can be interesting,

     I've had to use the SERDES in the FPGA IOB before now to oversample and edge detect the clock / data .

 

If you let us know what the adc and dac are we might be able to help more.

 

 

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