differential to single ended clock

[ramya2013]

Hi,

Im am using the VC707 kit. It only provides differential clock sources. Can I connect a single ended clock to either SYSCLOCK_P or  SYSCLOCK_N?

[smarell]

If you want to connect a differential clock source to a single-ended clock in the design then you need to use the P pin.

You need to connect SYSCLOCK_P to the single-ended clock in your design.

[umamahe]

You can use SYSCLOCK_P. But please o note that Signle ended IO standard to be define in UCF and recompilation of project requuire.

[mcgett]

> Can I connect a single ended clock to either SYSCLOCK_P or  SYSCLOCK_N?

On the VC707 that you are using the SYSCLK_P and SYSCLK_N are connected to a differential clock oscillator (U51  - SIT9102 @ 200 MHz).  You MUST use a LVDS input buffer for this input and if you attempt to use a single ended IOSTANDARD (LVCMOS15 as VCCO for bank 38 is 1.5V) the electrical levels will not be compatible and the clock in the FPGA will be a constant logic high value.

[muzaffer]

sysclk_p/n nets have a device attached to them already and this is soldered on the board so it would be difficult to replace this with a single ended clock. If you are willing to remove the oscillator (and probably the 100 ohm termination resistor) you can apply a 1.5V external clock to the sysclk_p net.
It would be much easier to apply a single ended clock to the user_sma_clock_p connector.

[aslsfr]

Hi;

I'm need to connect an 250 Mhz Signal generator toVC707 and my UUT to syncronize the clocks. İs it possible to do this on VC707? The clock from Signal generator is single ended.  I'm new at Vivado. How can I also configure this on the VHDL side?

[billhunter]

Congrats on resurrecting an 8 year old thread. Connect to J31 User_clk_p, and define a single ended clock in your design. in the constraints, the clock is pin AJ32, and the type is 1.8V LVCMOS,

set_property PACKAGE_PIN AJ32 [get_ports myclock]
set_property IOSTANDARD LVCMOS18 [get_ports myclock]

When connecting your external clock be very careful to not drive the signal negative or exceed the 1.8V rail. A signal level of 10 to 15 dBm (18dBm absolute max) should suffice, and either an offset of 0.9V or AC coupled.

[aslsfr]

Thanks for your kind reply. according to your reply will fpga use a single ended clock? Is it relibale caompared to differential clock. Is there a way to convert the single ended clock to diffential and use the differential clock, without using any external resource?

[muzaffer]

There are no internal differential clocks in the FPGA. If you have an external differential clock source you can use it but you still have to convert it to a single ended signal at the IO boundary of the FPGA (using a differential IO buffer)

[billhunter]

From what you describe, you have a signal generator, which is single ended, and an FPGA board that is single ended. There is no need to convert it to differential. Single ended will be more reliable given your set up. If you really want differential, then you need to add a balun to the cable coming from the signal generator, then you need to convert the differential output from the balun into two single ended lines and tie the grounds of these single ended lines together at the balun. The single ended lines then plug into the complementary pair on the FPGA. Since all the lines need to be 50 ohm, the power level at the FPGA will be 1/2 that leaving the signal generator, so the siggen will need to take that into account. All this should probably be done on a RF PCB board, and should be designed by an RF engineer or someone with RF experience. The FPGA needs to use internal terminations and have the right IO standard set up. Then again, you can simply use single ended and be off and rolling in an hour.