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Visitor asmatia
Visitor
1,380 Views
Registered: ‎03-13-2018

drive clock out from FPGA

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I have LVDS input clock connected to my FPGA (regular IO LVDS input). I also have LVDS output pins connected to external connector. I want to drive the input LVDS clock to the connector. what is the best method of "shorting" the input to the output without adding too much jitter?

1 Solution

Accepted Solutions
Moderator
Moderator
1,608 Views
Registered: ‎08-08-2017

Re: drive clock out from FPGA

Jump to solution

Hi @asmatia 

 

I believe your objective here is only to forward the clock  .Use below chain of primitives

 

IBUFDS -> BUFG -> MMCM -> ODDR -> OBUFDS.

 

ODDR is to  keeps the duty cycle and provides the best possible path[Assign Logic '1'  to D1 and  Logic '0' to D2. [This way, the output of the ODDR will generate a high at posedge of the clock and a low at negedge of the clock]

 

If you are using 7 series device , Please refer to the 7 series FPGA Libraries Guide for description and instantiation of these primitives

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug953-vivado-7series-libraries.pdf 

 

For ultrascale device , refer UG974 [UltraScale Architecture Libraries Guide]

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug974-vivado-ultrascale-libraries.pdf

 

------------------------------------------------------------------------------------------------------------------------------------------------------------------

Please reply if you have any queries , Give Kudos and Accept as Solution if you get the resolution of your queries.

------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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2 Replies
Moderator
Moderator
1,609 Views
Registered: ‎08-08-2017

Re: drive clock out from FPGA

Jump to solution

Hi @asmatia 

 

I believe your objective here is only to forward the clock  .Use below chain of primitives

 

IBUFDS -> BUFG -> MMCM -> ODDR -> OBUFDS.

 

ODDR is to  keeps the duty cycle and provides the best possible path[Assign Logic '1'  to D1 and  Logic '0' to D2. [This way, the output of the ODDR will generate a high at posedge of the clock and a low at negedge of the clock]

 

If you are using 7 series device , Please refer to the 7 series FPGA Libraries Guide for description and instantiation of these primitives

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug953-vivado-7series-libraries.pdf 

 

For ultrascale device , refer UG974 [UltraScale Architecture Libraries Guide]

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug974-vivado-ultrascale-libraries.pdf

 

------------------------------------------------------------------------------------------------------------------------------------------------------------------

Please reply if you have any queries , Give Kudos and Accept as Solution if you get the resolution of your queries.

------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Visitor asmatia
Visitor
1,366 Views
Registered: ‎03-13-2018

Re: drive clock out from FPGA

Jump to solution

thanks!! very helpfull!!

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